... | @@ -7,9 +7,15 @@ This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA |
... | @@ -7,9 +7,15 @@ This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA |
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connectivity and fail-safe functionality. The card has been developed
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connectivity and fail-safe functionality. The card has been developed
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within CERN's [TE-ABT
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within CERN's [TE-ABT
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group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
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group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
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for the Fast Interlocks Detection System (FIDS). It has memory and
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for the Fast Interlocks Detection System (FIDS) project. The main
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clocking resources and supports the White Rabbit timing and control
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controller is a System-on-a-Chip from Xilinx®, the Zynq XCZ030 that
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network. Stand-alone board for use in a 'pizza-box'.
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consists of two silicon ARM (R) cores and FPGA fabric. The idea is to
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implement fast interlocking logic (\<100ns) in the FPGA while the
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processor, running Embedded GNU/Linux, runs user applications to control
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the equipment and communicate with other devices and CERN's Controls
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MiddelWare (CMW). Additionally there is DDR3L memory, clocking resources
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and support the White Rabbit timing and control network. Stand-alone
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board for use in a 'pizza-box'.
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*TEMPLATE, PLEASE
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*TEMPLATE, PLEASE
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MODIFY**
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MODIFY**
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