... | @@ -99,7 +99,11 @@ Specifications |
... | @@ -99,7 +99,11 @@ Specifications |
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*Latest:**
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*Latest:**
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- Hardware: <http://edms.cern.ch/nav/EDA-03288-V1-0>
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- Hardware:
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- V1 prototype (2 produced)
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<http://edms.cern.ch/nav/EDA-03288-V1-0>
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- V2 pre-series (10 produced)
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http://edms.cern.ch/nav/EDA-03288-V2-0":http://edms.cern.ch/nav/EDA-03288-V2-0
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- Gateware:
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- Gateware:
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- [See this project's
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- [See this project's
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repository](https://www.ohwr.org/project/fasec/tree/master)
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repository](https://www.ohwr.org/project/fasec/tree/master)
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... | @@ -188,17 +192,17 @@ Unchanged: |
... | @@ -188,17 +192,17 @@ Unchanged: |
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<td>Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer</td>
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<td>Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>14-04-2017</td>
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<td>14-08-2017</td>
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<td><em>Full board validated in operation, implement 2nd iteration schematics & PCB</em></td>
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<td>Full board validated in operation, implement 2nd iteration schematics & PCB</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>12-06-2017</td>
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<td>11-09-2017</td>
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<td><em>Order pre-series production (10x)</em></td>
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<td>Pre-series production ordered (10x)</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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-----
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-----
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19 April 2016
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07 September 2017
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