... | ... | @@ -9,9 +9,9 @@ The card has been developed within CERN's [TE-ABT |
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group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
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for the Fast Interlocks Detection System (FIDS) project.
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The main controller is a System-on-a-Chip from Xilinx®, the Zynq XCZ030
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that consists of two silicon ARM (R) cores and FPGA fabric. The idea is
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to implement fast interlocking logic (\<100ns) in the FPGA while the
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The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030
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that consists of two silicon ARM cores and FPGA fabric. The idea is to
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implement fast interlocking logic (\<100ns) in the FPGA while the
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processor, running Embedded GNU/Linux, runs user applications to control
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deterministically the equipment and communicate with other devices and
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CERN's Controls MiddleWare (CMW). Additionally there is DDR3L memory,
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