Commit a615cede authored by David Cussans's avatar David Cussans

Checking old manufacturing files into repo

parent 8eca0438
......@@ -5,7 +5,7 @@
pc051
Version = C
Subversion = 201
Subversion = 206
This file describes PCB fabrication details of a board with eight 8-channel
14-bit 40MSample/s ADC + FPGA for SoLiD readout.
......@@ -69,12 +69,12 @@ pc051c_DD.art
Drill information ( Excellon format, described in nc_param.txt )
----------------------------------------------------------------
pc051c_toplevel_201-1-6.drl
pc051c_toplevel_206-1-6.drl
Router information ( Excellon format )
--------------------------------------
pc051c_toplevel_201.rou
pc051c_toplevel_206.rou
Bill of Materials
-----------------
......@@ -95,13 +95,13 @@ ODB++ Information
PCB fabrication and assembly data are contained in the ODB++ file:
pc051c_201.tgz
pc051c_206.tgz
IPC-2581
--------
PCB fabrication and assembly data are contained in the IPC-2581 file:
pc051c_toplevel_ipc2581_201.xml
pc051c_toplevel_ipc2581_206.xml
......@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : pc051c_toplevel_205.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 12:24:12 2017 )
( Date/Time : Tue Apr 25 14:09:31 2017 )
( )
(---------------------------------------------------------------------)
......
......@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : pc051c_toplevel_204.brd )
( Drawing : pc051c_toplevel_205.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 08:54:49 2017 )
( Date/Time : Tue Apr 25 10:00:13 2017 )
( )
(---------------------------------------------------------------------)
......
......@@ -4,7 +4,7 @@
( )
( Drawing : pc051c_toplevel_205.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 10:00:13 2017 )
( Date/Time : Tue Apr 25 12:21:55 2017 )
( )
(---------------------------------------------------------------------)
......@@ -20,7 +20,7 @@
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... Total number of DRC errors 9
..... DRC update completed, total CPU time 0:00:02
*************************************************************************
......
......@@ -4,7 +4,7 @@
( )
( Drawing : pc051c_toplevel_205.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 12:21:55 2017 )
( Date/Time : Tue Apr 25 12:24:12 2017 )
( )
(---------------------------------------------------------------------)
......@@ -20,7 +20,7 @@
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 9
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:02
*************************************************************************
......
......@@ -2,14 +2,12 @@
( )
( DBDOCTOR )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:15:38 2017 )
( Date/Time : Tue Apr 25 14:36:56 2017 )
( )
(---------------------------------------------------------------------)
WARNING WARNING(SPMHDB-42): Run batch DRC to correctly regenerate DRC errs.
1 warnings, 0 errors detected, 0 errors could be fixed.
0 warnings, 0 errors detected, 0 errors could be fixed.
......@@ -2,15 +2,12 @@
( )
( DBDOCTOR )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:08:29 2017 )
( Date/Time : Tue Apr 25 14:13:03 2017 )
( )
(---------------------------------------------------------------------)
ERROR IN T location = (143.5500 393.6500)
WARNING(SPMHA1-91): Illegal connection.
0 warnings, 1 errors detected, 0 errors could be fixed.
0 warnings, 0 errors detected, 0 errors could be fixed.
......@@ -2,18 +2,12 @@
( )
( DBDOCTOR )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:12:52 2017 )
( Date/Time : Tue Apr 25 14:15:27 2017 )
( )
(---------------------------------------------------------------------)
ERROR IN T location = (143.5500 393.6500)
WARNING(SPMHA1-91): Illegal connection.
Error was fixed.
WARNING WARNING(SPMHDB-42): Run batch DRC to correctly regenerate DRC errs.
1 warnings, 1 errors detected, 1 errors fixed.
0 warnings, 0 errors detected, 0 errors could be fixed.
......@@ -2,14 +2,12 @@
( )
( DBDOCTOR )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:13:20 2017 )
( Date/Time : Tue Apr 25 14:24:07 2017 )
( )
(---------------------------------------------------------------------)
WARNING WARNING(SPMHDB-42): Run batch DRC to correctly regenerate DRC errs.
1 warnings, 0 errors detected, 0 errors could be fixed.
0 warnings, 0 errors detected, 0 errors could be fixed.
......@@ -2,20 +2,64 @@
| ECO REPORT |
| Page 1 |
|------------------------------------------------------------------------------|
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_203.brd |
| Mon Apr 24 12:04:55 2017 |
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd |
| Tue Apr 25 13:03:51 2017 |
|------------------------------------------------------------------------------|
| NET CHANGES |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| net name | type of change | pin_id | x | y | to net |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
P3V3 pins MOVED FROM this net (to net name listed on right)
C48.2 155.200 154.050
P2V5
C49.2 151.500 154.050
P2V5
FPGA_JTAG_VREF pins ADDED TO this existing net (pins not previously on any net)
LK22.1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
GPIO<8> pins ADDED TO this existing net (pins not previously on any net)
LK23.1
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 2 |
|------------------------------------------------------------------------------|
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd |
| Tue Apr 25 13:03:51 2017 |
|------------------------------------------------------------------------------|
| COMPONENTS ADDED to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| ref des | device type |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
LK22 1-HOLE_0-4-BASE
LK23 1-HOLE_0-4-BASE
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 3 |
|------------------------------------------------------------------------------|
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd |
| Tue Apr 25 13:03:51 2017 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
LK22.1 PRIM_FILE /projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_connectors/1#2dhole/chips/chips.prt
LK22.1 SIZE 1
LK23.1 PRIM_FILE /projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/cds_connectors/1#2dhole/chips/chips.prt
LK23.1 SIZE 1
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 4 |
|------------------------------------------------------------------------------|
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd |
| Tue Apr 25 13:03:51 2017 |
|------------------------------------------------------------------------------|
| PIN PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| pin_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
LK22.1 CDS_PINID A(0)
LK23.1 CDS_PINID A(0)
|------------------------------------------------------------------------------|
| Nets changed : 2 |
| Components added : 2 |
| Pin property added : 2 |
| Slot property added : 4 |
| |
| Total ECO changes reported: 2 |
| Total ECO changes reported: 10 |
|------------------------------------------------------------------------------|
......@@ -2,16 +2,20 @@
| ECO REPORT |
| Page 1 |
|------------------------------------------------------------------------------|
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_202.brd |
| Mon Apr 24 11:21:19 2017 |
| .../design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_203.brd |
| Mon Apr 24 12:04:55 2017 |
|------------------------------------------------------------------------------|
| NET CHANGES |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| net name | type of change | pin_id | x | y | to net |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
UNNAMED_2_CAPCERSMDCL2_I187_B net RENAMED (to net name listed on right) P5V_FPGA
P3V3 pins MOVED FROM this net (to net name listed on right)
C48.2 155.200 154.050
P2V5
C49.2 151.500 154.050
P2V5
|------------------------------------------------------------------------------|
| Nets changed : 1 |
| Nets changed : 2 |
| |
| Total ECO changes reported: 1 |
| Total ECO changes reported: 2 |
|------------------------------------------------------------------------------|
# sum_view.txt
#
# edit history:
# ddd 03/08/88 Initial version.
# Property of Cadence Design Systems, Inc. All rights reserved.
#
# $Header: cmp_rep_view.txt.v 1.1 12/01/87 ddd Prealpha
#
# File: cmp_rep_view.txt - Component data extract cmd file for
# component list report
#
# Revision history:
# (0.10) ddd 12/01/87 Preliminary initial version
#
#
COMPONENT
#
# Extract: refdes(sort), refdes, device_type, value, tolerance,
# package, x, y, angle, mirror.
#
REFDES_SORT
REFDES
COMP_DEVICE_TYPE
COMP_VALUE
COMP_TOL
COMP_PACKAGE
SYM_X
SYM_Y
SYM_ROTATE
SYM_MIRROR
#
# end of cmp_rep_view
#
# note:
# no fields are allowed in this "view"
SUMMARY
# sum_view.txt
#
# Property of Cadence Design Systems, Inc. All rights reserved.
#
# $Header: cmp_rep_view.txt.v 1.1 12/01/87 ddd Prealpha
#
# File: cmp_rep_view.txt - Component data extract cmd file for
# component list report
#
# Revision history:
# (0.10) ddd 12/01/87 Preliminary initial version
#
#
COMPONENT
#
# Extract: refdes(sort), refdes, device_type, value, tolerance,
# package, x, y, angle, mirror.
#
REFDES_SORT
REFDES
COMP_DEVICE_TYPE
COMP_VALUE
COMP_TOL
COMP_PACKAGE
SYM_X
SYM_Y
SYM_ROTATE
SYM_MIRROR
#
# end of cmp_rep_view
# edit history:
# ddd 03/08/88 Initial version.
#
# note:
# no fields are allowed in this "view"
SUMMARY
# sum_view.txt
#
# edit history:
# ddd 03/08/88 Initial version.
# Property of Cadence Design Systems, Inc. All rights reserved.
#
# $Header: cmp_rep_view.txt.v 1.1 12/01/87 ddd Prealpha
#
# File: cmp_rep_view.txt - Component data extract cmd file for
# component list report
#
# Revision history:
# (0.10) ddd 12/01/87 Preliminary initial version
#
#
COMPONENT
#
# Extract: refdes(sort), refdes, device_type, value, tolerance,
# package, x, y, angle, mirror.
#
REFDES_SORT
REFDES
COMP_DEVICE_TYPE
COMP_VALUE
COMP_TOL
COMP_PACKAGE
SYM_X
SYM_Y
SYM_ROTATE
SYM_MIRROR
#
# end of cmp_rep_view
#
# note:
# no fields are allowed in this "view"
SUMMARY
......@@ -3,7 +3,7 @@
( IPC2581 Export )
( )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:19:01 2017 )
( Date/Time : Tue Apr 25 14:19:28 2017 )
( )
(---------------------------------------------------------------------)
......@@ -14,10 +14,6 @@ Collecting net list ...
Collecting padstack defintions ...
Collecting package defintions ...
WARNING: No PLACE_BOUND outline found for the package "BRISTOL_LOGO_OUTLINE", IGNORED.
......@@ -35,11 +31,10 @@ Collecting BOM items ...
Property configuration file: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/ipc2581_attr_config.atr
IPC2581 file: pc051c_toplevel_201
IPC2581 version: IPC2581-B
BRD file: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_201.brd
IPC2581 file: pc051c_toplevel_206
IPC2581 version: IPC2581-A
BRD file: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_206.brd
IPC2581 units: MILLIMETER
Global package pin1 orientation: OTHER
Default symbol height: 3.81
Export drill information?: YES
Export BOM information?: YES
......@@ -56,6 +51,6 @@ Export Miscellaneous Image Layers?: YES
Export SolderMask/SolderPaste Legend Layers?: YES
Export vector text?: YES
Export cavities?: NO
Export padstack definitions?: YES
Export padstack definitions?: NO
Export zip file?: NO
a2ipc2581 complete.
0.2000 P T01 0.000000 0.000000
0.3302 P T02 0.000000 0.000000
0.4064 P T03 0.000000 0.000000
0.8128 P T04 0.000000 0.000000
0.8500 P T05 0.000000 0.000000
0.9000 P T06 0.000000 0.000000
0.9144 P T07 0.000000 0.000000
0.9500 P T08 0.000000 0.000000
1.0000 P T09 0.000000 0.000000
1.0160 P T10 0.000000 0.000000
1.0500 P T11 0.000000 0.000000
1.3500 P T12 0.000000 0.000000
1.4000 P T13 0.000000 0.000000
1.7000 P T14 0.000000 0.000000
2.7000 P T15 0.000000 0.000000
2.8000 P T16 0.000000 0.000000
3.3020 P T17 0.000000 0.000000
1.4500 N T18 0.000000 0.000000
1.5500 N T19 0.000000 0.000000
1.7000 N T20 0.000000 0.000000
1.9500 N T21 0.000000 0.000000
0.5000 P T04 0.000000 0.000000
0.8128 P T05 0.000000 0.000000
0.8500 P T06 0.000000 0.000000
0.9000 P T07 0.000000 0.000000
0.9144 P T08 0.000000 0.000000
0.9500 P T09 0.000000 0.000000
1.0000 P T10 0.000000 0.000000
1.0160 P T11 0.000000 0.000000
1.0500 P T12 0.000000 0.000000
1.3500 P T13 0.000000 0.000000
1.4000 P T14 0.000000 0.000000
1.7000 P T15 0.000000 0.000000
2.7000 P T16 0.000000 0.000000
2.8000 P T17 0.000000 0.000000
3.3020 P T18 0.000000 0.000000
1.4500 N T19 0.000000 0.000000
1.5500 N T20 0.000000 0.000000
1.7000 N T21 0.000000 0.000000
1.9500 N T22 0.000000 0.000000
......@@ -2,9 +2,9 @@
( )
( NC DRILL Log )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:14:16 2017 )
( Date/Time : Tue Apr 25 14:17:27 2017 )
( )
(---------------------------------------------------------------------)
......@@ -73,14 +73,14 @@
'pc051c_toplevel_201-1-6.drl' created for holes connecting TOP and BOTTOM
'pc051c_toplevel_206-1-6.drl' created for holes connecting TOP and BOTTOM
-------------------------------------------------------------------------
Tool Num Size +/- Tolerance Plating Quantity
T01 1. 0.2000 0.0000/ 0.0000 PLATED 896
T02 2. 0.3302 0.0000/ 0.0000 PLATED 1304
T03 3. 0.4064 0.0000/ 0.0000 PLATED 411
T02 2. 0.3302 0.0000/ 0.0000 PLATED 1307
T03 3. 0.4064 0.0000/ 0.0000 PLATED 416
T04 4. 0.5000 0.0000/ 0.0000 PLATED 97
T05 5. 0.8128 0.0000/ 0.0000 PLATED 17
T06 6. 0.8500 0.0000/ 0.0000 PLATED 2
......@@ -101,7 +101,7 @@
T21 21. 1.7000 0.0000/ 0.0000 NON_PLATED 4
T22 22. 1.9500 0.0000/ 0.0000 NON_PLATED 12
---- Total holes: 3299
---- Total holes: 3307
---- Total head travel: 395.61 feet (120.58 meters)
---- Total head travel: 405.52 feet (123.60 meters)
......@@ -2,9 +2,9 @@
( )
( NC DRILL Log )
( )
( Drawing : pc051b_toplevel_162.brd )
( Drawing : pc051b_toplevel_163.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Thu Sep 8 15:36:04 2016 )
( Date/Time : Fri Sep 9 12:35:23 2016 )
( )
(---------------------------------------------------------------------)
......@@ -73,7 +73,7 @@
'pc051b_toplevel_162-1-6.drl' created for holes connecting TOP and BOTTOM
'pc051b_toplevel_163-1-6.drl' created for holes connecting TOP and BOTTOM
-------------------------------------------------------------------------
Tool Num Size +/- Tolerance Plating Quantity
......
......@@ -2,9 +2,9 @@
( )
( NC DRILL Log )
( )
( Drawing : pc051b_toplevel_163.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Fri Sep 9 12:35:23 2016 )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:06:28 2016 )
( )
(---------------------------------------------------------------------)
......@@ -62,18 +62,17 @@
2.7000 P T15 0.000000 0.000000
2.8000 P T16 0.000000 0.000000
3.3020 P T17 0.000000 0.000000
1.4000 N T18 0.000000 0.000000
1.4500 N T19 0.000000 0.000000
1.5500 N T20 0.000000 0.000000
1.7000 N T21 0.000000 0.000000
1.9500 N T22 0.000000 0.000000
1.4500 N T18 0.000000 0.000000
1.5500 N T19 0.000000 0.000000
1.7000 N T20 0.000000 0.000000
1.9500 N T21 0.000000 0.000000
Drill files being output to directory '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051b_toplevel/physical' ...
Drill files being output to directory 'P:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051b_toplevel/physical' ...
'pc051b_toplevel_163-1-6.drl' created for holes connecting TOP and BOTTOM
'pc051b_toplevel_165-1-6.drl' created for holes connecting TOP and BOTTOM
-------------------------------------------------------------------------
Tool Num Size +/- Tolerance Plating Quantity
......@@ -95,13 +94,12 @@
T15 15. 2.7000 0.0000/ 0.0000 PLATED 6
T16 16. 2.8000 0.0000/ 0.0000 PLATED 8
T17 17. 3.3020 0.0000/ 0.0000 PLATED 4
T18 18. 1.4000 0.0000/ 0.0000 NON_PLATED 2
T19 19. 1.4500 0.0000/ 0.0000 NON_PLATED 6
T20 20. 1.5500 0.0000/ 0.0000 NON_PLATED 4
T21 21. 1.7000 0.0000/ 0.0000 NON_PLATED 2
T22 22. 1.9500 0.0000/ 0.0000 NON_PLATED 12
T18 18. 1.4500 0.0000/ 0.0000 NON_PLATED 6
T19 19. 1.5500 0.0000/ 0.0000 NON_PLATED 4
T20 20. 1.7000 0.0000/ 0.0000 NON_PLATED 4
T21 21. 1.9500 0.0000/ 0.0000 NON_PLATED 12
---- Total holes: 3258
---- Total head travel: 392.64 feet (119.68 meters)
---- Total head travel: 391.22 feet (119.24 meters)
......@@ -2,9 +2,9 @@
( )
( NC DRILL Log )
( )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:06:28 2016 )
( Drawing : pc051c_toplevel_201.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:14:16 2017 )
( )
(---------------------------------------------------------------------)
......@@ -48,58 +48,60 @@
0.2000 P T01 0.000000 0.000000
0.3302 P T02 0.000000 0.000000
0.4064 P T03 0.000000 0.000000
0.8128 P T04 0.000000 0.000000
0.8500 P T05 0.000000 0.000000
0.9000 P T06 0.000000 0.000000
0.9144 P T07 0.000000 0.000000
0.9500 P T08 0.000000 0.000000
1.0000 P T09 0.000000 0.000000
1.0160 P T10 0.000000 0.000000
1.0500 P T11 0.000000 0.000000
1.3500 P T12 0.000000 0.000000
1.4000 P T13 0.000000 0.000000
1.7000 P T14 0.000000 0.000000
2.7000 P T15 0.000000 0.000000
2.8000 P T16 0.000000 0.000000
3.3020 P T17 0.000000 0.000000
1.4500 N T18 0.000000 0.000000
1.5500 N T19 0.000000 0.000000
1.7000 N T20 0.000000 0.000000
1.9500 N T21 0.000000 0.000000
Drill files being output to directory 'P:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051b_toplevel/physical' ...
'pc051b_toplevel_165-1-6.drl' created for holes connecting TOP and BOTTOM
0.5000 P T04 0.000000 0.000000
0.8128 P T05 0.000000 0.000000
0.8500 P T06 0.000000 0.000000
0.9000 P T07 0.000000 0.000000
0.9144 P T08 0.000000 0.000000
0.9500 P T09 0.000000 0.000000
1.0000 P T10 0.000000 0.000000
1.0160 P T11 0.000000 0.000000
1.0500 P T12 0.000000 0.000000
1.3500 P T13 0.000000 0.000000
1.4000 P T14 0.000000 0.000000
1.7000 P T15 0.000000 0.000000
2.7000 P T16 0.000000 0.000000
2.8000 P T17 0.000000 0.000000
3.3020 P T18 0.000000 0.000000
1.4500 N T19 0.000000 0.000000
1.5500 N T20 0.000000 0.000000
1.7000 N T21 0.000000 0.000000
1.9500 N T22 0.000000 0.000000
Drill files being output to directory '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical' ...
'pc051c_toplevel_201-1-6.drl' created for holes connecting TOP and BOTTOM
-------------------------------------------------------------------------
Tool Num Size +/- Tolerance Plating Quantity
T01 1. 0.2000 0.0000/ 0.0000 PLATED 896
T02 2. 0.3302 0.0000/ 0.0000 PLATED 1367
T02 2. 0.3302 0.0000/ 0.0000 PLATED 1304
T03 3. 0.4064 0.0000/ 0.0000 PLATED 411
T04 4. 0.8128 0.0000/ 0.0000 PLATED 12
T05 5. 0.8500 0.0000/ 0.0000 PLATED 2
T06 6. 0.9000 0.0000/ 0.0000 PLATED 2
T07 7. 0.9144 0.0000/ 0.0000 PLATED 49
T08 8. 0.9500 0.0000/ 0.0000 PLATED 18
T09 9. 1.0000 0.0000/ 0.0000 PLATED 400
T10 10. 1.0160 0.0000/ 0.0000 PLATED 20
T11 11. 1.0500 0.0000/ 0.0000 PLATED 20
T12 12. 1.3500 0.0000/ 0.0000 PLATED 4
T13 13. 1.4000 0.0000/ 0.0000 PLATED 5
T14 14. 1.7000 0.0000/ 0.0000 PLATED 8
T15 15. 2.7000 0.0000/ 0.0000 PLATED 6
T16 16. 2.8000 0.0000/ 0.0000 PLATED 8
T17 17. 3.3020 0.0000/ 0.0000 PLATED 4
T18 18. 1.4500 0.0000/ 0.0000 NON_PLATED 6
T19 19. 1.5500 0.0000/ 0.0000 NON_PLATED 4
T20 20. 1.7000 0.0000/ 0.0000 NON_PLATED 4
T21 21. 1.9500 0.0000/ 0.0000 NON_PLATED 12
---- Total holes: 3258
---- Total head travel: 391.22 feet (119.24 meters)
T04 4. 0.5000 0.0000/ 0.0000 PLATED 97
T05 5. 0.8128 0.0000/ 0.0000 PLATED 17
T06 6. 0.8500 0.0000/ 0.0000 PLATED 2
T07 7. 0.9000 0.0000/ 0.0000 PLATED 4
T08 8. 0.9144 0.0000/ 0.0000 PLATED 49
T09 9. 0.9500 0.0000/ 0.0000 PLATED 18
T10 10. 1.0000 0.0000/ 0.0000 PLATED 400
T11 11. 1.0160 0.0000/ 0.0000 PLATED 20
T12 12. 1.0500 0.0000/ 0.0000 PLATED 20
T13 13. 1.3500 0.0000/ 0.0000 PLATED 4
T14 14. 1.4000 0.0000/ 0.0000 PLATED 5
T15 15. 1.7000 0.0000/ 0.0000 PLATED 8
T16 16. 2.7000 0.0000/ 0.0000 PLATED 6
T17 17. 2.8000 0.0000/ 0.0000 PLATED 8
T18 18. 3.3020 0.0000/ 0.0000 PLATED 4
T19 19. 1.4500 0.0000/ 0.0000 NON_PLATED 6
T20 20. 1.5500 0.0000/ 0.0000 NON_PLATED 4
T21 21. 1.7000 0.0000/ 0.0000 NON_PLATED 4
T22 22. 1.9500 0.0000/ 0.0000 NON_PLATED 12
---- Total holes: 3299
---- Total head travel: 395.61 feet (120.58 meters)
......@@ -2,16 +2,16 @@
( )
( DRILL LEGEND )
( )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:03:41 2016 )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 14:10:23 2017 )
( )
(---------------------------------------------------------------------)
Begin processing of drill legend template file 'C:/Cadence/SPB_16.6/share/pcb/text/nclegend/default-mm.dlt' ...
Begin processing of drill legend template file '/eda/cadence/2016-17/RHELx86/SPB_16.60.079/share/pcb/text/nclegend/default-mm.dlt' ...
End of drill legend template file processing.
Begin processing drill holes.
No errors detected in processing holes.
Warning : Hole 0.8128-0.0000-C-P-0.0000-0.0000 uses multiple drill figures.
End processing drill holes.
......@@ -2,16 +2,13 @@
( )
( DRILL LEGEND )
( )
( Drawing : pc051b_toplevel_46.brd )
( Software Version : 16.6S035 )
( Date/Time : Tue Dec 1 17:39:51 2015 )
( Drawing : pc051b_toplevel_139.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Aug 05 18:17:43 2016 )
( )
(---------------------------------------------------------------------)
Begin processing of drill legend template file '/software/CAD/Cadence/2014_2015/SPB166/share/pcb/text/nclegend/default-mm.dlt' ...
Begin processing of drill legend template file 'C:/Cadence/SPB_16.6/share/pcb/text/nclegend/default-mm.dlt' ...
End of drill legend template file processing.
Begin processing drill holes.
No errors detected in processing holes.
End processing drill holes.
Drill Legend command cancelled.
......@@ -2,13 +2,16 @@
( )
( DRILL LEGEND )
( )
( Drawing : pc051b_toplevel_139.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Aug 05 18:17:43 2016 )
( Drawing : pc051b_toplevel_162.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Thu Sep 8 15:35:39 2016 )
( )
(---------------------------------------------------------------------)
Begin processing of drill legend template file 'C:/Cadence/SPB_16.6/share/pcb/text/nclegend/default-mm.dlt' ...
Begin processing of drill legend template file '/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/pcb/text/nclegend/default-mm.dlt' ...
End of drill legend template file processing.
Drill Legend command cancelled.
Begin processing drill holes.
No errors detected in processing holes.
End processing drill holes.
......@@ -2,14 +2,14 @@
( )
( DRILL LEGEND )
( )
( Drawing : pc051b_toplevel_162.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Thu Sep 8 15:35:39 2016 )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:03:41 2016 )
( )
(---------------------------------------------------------------------)
Begin processing of drill legend template file '/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/pcb/text/nclegend/default-mm.dlt' ...
Begin processing of drill legend template file 'C:/Cadence/SPB_16.6/share/pcb/text/nclegend/default-mm.dlt' ...
End of drill legend template file processing.
Begin processing drill holes.
......
......@@ -2,9 +2,9 @@
( )
( NC ROUTE Log )
( )
( Drawing : pc051c_toplevel_201.brd )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:14:36 2017 )
( Date/Time : Tue Apr 25 14:18:01 2017 )
( )
(---------------------------------------------------------------------)
......@@ -59,7 +59,7 @@
-------------------------------------------------------------
NC Route file 'pc051c_toplevel_201.rou' created ...
NC Route file 'pc051c_toplevel_206.rou' created ...
-------------------------------------------------------------
......
......@@ -2,9 +2,9 @@
( )
( NC ROUTE Log )
( )
( Drawing : pc051b_toplevel_162.brd )
( Drawing : pc051b_toplevel_163.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Thu Sep 8 15:36:19 2016 )
( Date/Time : Fri Sep 9 12:35:39 2016 )
( )
(---------------------------------------------------------------------)
......@@ -59,7 +59,7 @@
-------------------------------------------------------------
NC Route file 'pc051b_toplevel_162.rou' created ...
NC Route file 'pc051b_toplevel_163.rou' created ...
-------------------------------------------------------------
......
......@@ -2,9 +2,9 @@
( )
( NC ROUTE Log )
( )
( Drawing : pc051b_toplevel_163.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Fri Sep 9 12:35:39 2016 )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:07:21 2016 )
( )
(---------------------------------------------------------------------)
......@@ -59,7 +59,7 @@
-------------------------------------------------------------
NC Route file 'pc051b_toplevel_163.rou' created ...
NC Route file 'pc051b_toplevel_165.rou' created ...
-------------------------------------------------------------
......
......@@ -2,9 +2,9 @@
( )
( NC ROUTE Log )
( )
( Drawing : pc051b_toplevel_165.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Sep 09 17:07:21 2016 )
( Drawing : pc051c_toplevel_201.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Fri Apr 21 17:14:36 2017 )
( )
(---------------------------------------------------------------------)
......@@ -59,7 +59,7 @@
-------------------------------------------------------------
NC Route file 'pc051b_toplevel_165.rou' created ...
NC Route file 'pc051c_toplevel_201.rou' created ...
-------------------------------------------------------------
......
......@@ -2,9 +2,9 @@
( )
( Allegro Netrev Import Logic )
( )
( Drawing : pc051c_toplevel_203.brd )
( Drawing : pc051c_toplevel_205.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Mon Apr 24 12:04:55 2017 )
( Date/Time : Tue Apr 25 13:03:51 2017 )
( )
(---------------------------------------------------------------------)
......@@ -19,17 +19,17 @@ Missing symbol has error: No
DRC update: Yes
Schematic directory: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged'
Design Directory: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical'
Old design name: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_203.brd'
New design name: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_204.brd'
Old design name: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd'
New design name: '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_206.brd'
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/pc051c_toplevel.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_203.brd /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_204.brd -w /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/temp/constraints_difference_report.xml -$
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/pc051c_toplevel.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_205.brd /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/pc051c_toplevel_206.brd -w /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/temp/constraints_difference_report.xml -$
------ Preparing to read pst files ------
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstchip.dat (00:00:00.06)
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstchip.dat (00:00:00.07)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstxprt.dat (00:00:00.01)
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstxprt.dat (00:00:00.02)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstxnet.dat (00:00:00.01)
......@@ -41,12 +41,12 @@ Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/
===========================================================
Start Constraint Diff3 Import
Constraint File: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstcmdb.dat
Allegro Baseline: /tmp/#Taaaaad10724.tmp
Allegro Baseline: /tmp/#Taaaaad21476.tmp
Schematic Baseline: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/packaged/pstcmbc.dat
Start time: Mon Apr 24 12:04:56 2017
Start time: Tue Apr 25 13:03:52 2017
===========================================================
===========================================================
Finished Constraint Update Time: Mon Apr 24 12:04:56 2017
Finished Constraint Update Time: Tue Apr 25 13:03:52 2017
===========================================================
------ Library Paths ------
......@@ -94,9 +94,9 @@ PADPATH = .
------ Summary Statistics ------
netrev run on Apr 24 12:04:55 2017
netrev run on Apr 25 13:03:51 2017
DESIGN NAME : 'PC051C_TOPLEVEL'
PACKAGING ON 24-Apr-2017 AT 12:04:46
PACKAGING ON 25-Apr-2017 AT 13:03:42
COMPILE 'logic'
CHECK_PIN_NAMES OFF
......
UUNITS = MILLIMETERS
U5 143.4000 373.7500 270 BGA256T16_100
J9 149.1000 206.1900 90 MOLEX_47082-001
J10 149.1000 176.1900 90 MOLEX_47082-001
J9 148.6900 206.1900 90 MOLEX_47082-001
J10 148.6900 176.1900 90 MOLEX_47082-001
U1 148.3102 149.8054 90 SOT23-5
U6 146.8602 112.5554 90 SOT23-5
U6 145.8202 112.5554 90 SOT23-5
IC13 151.1000 128.5950 0 SOIC127P600X175-16N
J19 94.3700 383.6700 90 AVX_00-8380-010-00X-0X-X
U7 48.4500 448.0000 180 SOT223_5
......@@ -373,7 +373,7 @@ C29 137.0000 405.4000 270 C0805
C3_10 136.7500 80.3000 90 C1210
C2 92.1500 255.0500 90 m C1210
C3 87.2500 255.2000 90 m C1210
C6 117.8000 441.5000 180 CAPC3225X279N
C6 114.8000 441.5000 0 CAPC3225X279N
C10 104.1000 436.4000 270 CAPC3225X279N
C12 100.7000 436.4000 270 CAPC3225X279N
C13 109.8000 426.4500 180 CAPC3225X279N
......@@ -383,8 +383,8 @@ C21 104.0000 405.9500 90 C1210
C23 91.6000 411.8000 90 C1210
C25 100.5500 405.9500 90 C1210
J17 140.0500 87.6000 90 CON14MD_2MM
J13 152.0500 144.5000 90 SAMTEC_HDMI-19-01-X-SM
J18 152.0500 114.5000 90 SAMTEC_HDMI-19-01-X-SM
J13 150.3100 144.5000 90 SAMTEC_HDMI-19-01-X-SM
J18 150.3100 114.5000 90 SAMTEC_HDMI-19-01-X-SM
J11 129.7000 270.7300 180 TYCO_1367073
J12 129.7000 244.9800 180 TYCO_1367073
J14 157.2500 396.3200 270 SAMTEC_TSW-102-23-L-S
......@@ -399,7 +399,7 @@ J2_10 133.8500 75.7000 180 CONHE13D3X1M
J4 137.5000 447.6500 180 CONHE13D3X1M
J5 137.5000 430.3500 180 CONHE13D3X1M
J6 137.5000 413.0000 180 CONHE13D3X1M
J3 120.5500 453.3000 270 CON4SL50890B
J3 105.3500 445.5000 90 CON4SL50890B
J7 3.0500 360.8000 180 HARTING_0903196X921
J8 3.0500 6.5000 180 HARTING_0903196X921
J15 3.0500 124.6000 180 HARTING_0903196X921
......
......@@ -2,17 +2,17 @@
( )
( PLCTXT Log )
( )
( Drawing : pc051b_toplevel_176.brd )
( Software Version : 16.6S037 )
( Date/Time : Thu Dec 08 12:46:15 2016 )
( Drawing : pc051c_toplevel_206.brd )
( Software Version : 16.6-2015S079 )
( Date/Time : Tue Apr 25 14:40:39 2017 )
( )
(---------------------------------------------------------------------)
Create a placement by text file: placement_pin1.txt
Create a placement by text file: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/placement_pin1.txt
Error retrieving pin 1 of U5 ... using origin instead
Error retrieving pin 1 of U8 ... using origin instead
Error retrieving pin 1 of IC6 ... using origin instead
......@@ -44,4 +44,4 @@
Error retrieving pin 1 of PL7 ... using origin instead
Successfully processed 762 placed components
Successfully processed 773 placed components
......@@ -2,46 +2,14 @@
( )
( PLCTXT Log )
( )
( Drawing : pc051b_toplevel_163.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Fri Sep 9 12:37:46 2016 )
( Drawing : pc051b_toplevel_173.brd )
( Software Version : 16.6-2015S058 )
( Date/Time : Fri Oct 14 13:36:00 2016 )
( )
(---------------------------------------------------------------------)
Create a placement by text file: placement_pin1.txt
Error retrieving pin 1 of U5 ... using origin instead
Error retrieving pin 1 of IC6 ... using origin instead
Error retrieving pin 1 of U1_1 ... using origin instead
Error retrieving pin 1 of U1_2 ... using origin instead
Error retrieving pin 1 of U1_3 ... using origin instead
Error retrieving pin 1 of U1_4 ... using origin instead
Error retrieving pin 1 of U1_6 ... using origin instead
Error retrieving pin 1 of U1_7 ... using origin instead
Error retrieving pin 1 of U1_8 ... using origin instead
Error retrieving pin 1 of U1_9 ... using origin instead
Error retrieving pin 1 of PL2 ... using origin instead
Error retrieving pin 1 of PL3 ... using origin instead
Error retrieving pin 1 of PL4 ... using origin instead
Error retrieving pin 1 of PL5 ... using origin instead
Error retrieving pin 1 of PL6 ... using origin instead
Error retrieving pin 1 of PL7 ... using origin instead
Create a placement by text file: place_txt.txt
Successfully processed 762 placed components
INFO: Reading report definition file '/eda/cadence/2016-17/RHELx86/SPB_16.60.079/share/pcb/signal/reports.dat'.
INFO: Finished reading report definition file successfully.
INFO: Reading report definition file '/eda/cadence/2016-17/RHELx86/SPB_16.60.079/share/pcb/signal/custom_rep.dat'.
INFO: Finished reading report definition file successfully.
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices.dml'
INFO: Loaded existing device file '/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051c_toplevel/physical/devices_dump.dml'
INFO: Finished loading SigNoise device libraries
INFO: Loaded existing interconnect file 'Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051c_toplevel\physical\interconn.iml'
INFO: Loaded existing interconnect file 'C:\CAD\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml'
INFO: Finished loading SigNoise interconnect libraries
INFO: Field Solver bem2d for STL_2S_1R_475
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaaf10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_476
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaag10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_477
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaah10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_478
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaai10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_479
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaaj10972.in" 0.00127
INFO: Field Solver bem2d for STL_2S_1R_480
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaak10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_481
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaal10972.in" 0.00127
INFO: Loaded existing interconnect file 'Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051c_toplevel\physical\interconn.iml'
INFO: Loaded existing interconnect file 'C:\CAD\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml'
INFO: Finished loading SigNoise interconnect libraries
INFO: Field Solver bem2d for STL_2S_1R_475
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaaf10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_476
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaag10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_477
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaah10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_478
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaai10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_479
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaaj10972.in" 0.00127
INFO: Field Solver bem2d for STL_2S_1R_480
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaak10972.in" 0.00127
INFO: Field Solver bem2d for STL_1S_1R_481
INFO: Executing command: bem2d 0 "C:/Users/phdgc/AppData/Local/Temp/#Taaaaal10972.in" 0.00127
INFO: Reading report definition file '/eda/cadence/2016-17/RHELx86/SPB_16.60.079/share/pcb/signal/reports.dat'.
INFO: Finished reading report definition file successfully.
INFO: Reading report definition file '/eda/cadence/2016-17/RHELx86/SPB_16.60.079/share/pcb/signal/custom_rep.dat'.
INFO: Finished reading report definition file successfully.
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