eb_slave_core: removed wishbone int signals

35bca79a · A. Hahn · d274abc3 · 35bca79a · 35bca79a · 35bca79a
Commit 35bca79a authored Jan 16, 2020 by A. Hahn
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Showing with 72 additions and 75 deletions

eb_cfg_fifo.vhd hdl/eb_slave_core/eb_cfg_fifo.vhd +22 -23

eb_eth_tx.vhd hdl/eb_slave_core/eb_eth_tx.vhd +40 -41

eb_slave_top.vhd hdl/eb_slave_core/eb_slave_top.vhd +10 -11

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--- a/hdl/eb_slave_core/eb_cfg_fifo.vhd
+++ b/hdl/eb_slave_core/eb_cfg_fifo.vhd
@@ -84,7 +84,6 @@ architecture rtl of eb_cfg_fifo is

 begin

-  cfg_o.int <= '0';
  cfg_o.err <= '0';
  cfg_o.rty <= '0';
  cfg_o.stall <= '0';

--- a/hdl/eb_slave_core/eb_eth_tx.vhd
+++ b/hdl/eb_slave_core/eb_eth_tx.vhd
@@ -135,7 +135,6 @@ begin
      r_dat_o(15 downto 0) => s_tx_dat);

  slave_o.ack <= r_ack;
-  slave_o.int <= '0';
  slave_o.rty <= '0';
  slave_o.err <= '0';
  slave_o.stall <= s_stall;

--- a/hdl/eb_slave_core/eb_slave_top.vhd
+++ b/hdl/eb_slave_core/eb_slave_top.vhd
@@ -92,7 +92,6 @@ begin
  EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall;
  EB_RX_o.err <= '0';
  EB_RX_o.rty <= '0';
-  EB_RX_o.int <= '0';
  EB_RX_o.stall <= rx_stall;
  EB_RX_o.dat <= (others => '0');