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# Wiki
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# Introduction
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Etherbone is an FPGA-core that connects Ethernet to internal on-chip
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wishbone buses permitting any core to talk to any other across Ethernet.
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A software library is provided that permits any computer with an
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Ethernet card to easily communicate with remote cores on the Etherbone
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network. The Etherbone core implements a wishbone master and a wishbone
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slave bus controller. With this scheme, any number of Etherbone
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FPGA-cores and application software tasks can be connected together to
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implement hybrid distributed networks of arbitrary complexity such as
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field-buses, timing systems, or testbeds for hardware debugging.
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Etherbone provides basic read, write and addressing functions. Etherbone
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data transfers are initiated either by FPGA cores connected to the
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Etherbone wishbone buses or by application software via the library. It
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is within in these Etherbone Accessible Devices (EAD) that specific
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cores may implement other levels of abstraction on top of Etherbone as
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required. More information is available in the [Document](/project/etherbone-core/wikis/Documents/Etherbone-core-functional-specifications) document.
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# Work so far
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>19-08-2010</td>
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<td>Project start.</td>
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</tr>
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<tr class="odd">
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<td>11-10-2010</td>
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<td>First functional spec draft released for comments.</td>
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</tr>
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</tbody>
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</table>
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# Outlook
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The target date for a first implementation is March 2011. The functional
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spec should be approved at the end of October 2010 and the technical
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spec should be ready by December 2010.
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... | | ... | |