... | @@ -14,7 +14,8 @@ data transfers are initiated either by FPGA cores connected to the |
... | @@ -14,7 +14,8 @@ data transfers are initiated either by FPGA cores connected to the |
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Etherbone wishbone buses or by application software via the library. It
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Etherbone wishbone buses or by application software via the library. It
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is within in these Etherbone Accessible Devices (EAD) that specific
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is within in these Etherbone Accessible Devices (EAD) that specific
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cores may implement other levels of abstraction on top of Etherbone as
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cores may implement other levels of abstraction on top of Etherbone as
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required. More information is available in the [Document](/project/etherbone-core/wikis/Documents/Etherbone-core-functional-specifications) document.
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required. More information is available in the [Document](/project/etherbone-core/wikis/Documents/Etherbone-core-functional-specifications) document.
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Ebinternals.png
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# Work so far
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# Work so far
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