eRTM14 Schematics & Layout Review

fpga_power
- extra wire at GND symbols and pin A1 on IC1M -> junctions
transceivers
- cannot open image from Matia's local home
- add len match directive for calibration resistor (UG476, p303)
gtx_data_splitter
- IC25, pin 5 extra wire -> junction
regulators
- LDOs have max dropout 400mV. Safer/more robust then to provide P1V5 and P3V8 instead of P1V4 and P3V7.
- T1, T3: INH/UVLO is connected through internal resistor divider to AGND. Should they (T1 and T3) also be connected to AGND ?
pll
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
clk_external
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- Diodes on TR3 secondary need refdes
sfp
- J3, J4, pins 9 and 31 extra wire -> junction

L6_PWR is dedicated to MP3V3 which takes about a half of the board, perhaps it could be also used for another power net?
L4_PWR: P2V5 has a strange shape, I suppose there were 2.5V pins in the bottom part that do not exist anymore
Top, L8: there are several single-ended clocks (CAL_CONTROL.SHIFTCLK, REF_CONTROl.UPDATECLK, LO_CONTROL.SHIFTCLK) routed together, perhaps there could be a larger distance between them to reduce EMI
Bottom: slightly misaligned vias (GND, X:183.4mm Y:209.2mm and X:183.4mm Y:206mm)
Bottom: extra vias for C84?
Bottom: extra via at X:123.575mm Y:134.2mm?
Bottom: swapping pins 2 and 3 in IC13 would make the connections shorter

General:
- Title blocks to be updated, add OHWR licenses.
Regulators:
- Add Pulldowns on power enable signals
- Change 3V7 to 3V8 and 1V4 to 1V6 to respect maximum dropout of the LDOs.
PLL:
- Missing ground on cdcm61002 decoupling caps
- IC6 CS pin should not be grounded!
- Add CS pin connections to the FPGA for both PLLs
LED_FP:
- don't use a PMOS to drive the LEDs (too high Vgson)
Other:
- Add pulldowns for VCXO enable inputs
- Remove XADC (seems to not be used at all)
- Add net ties on PP12V and MTCA_MP3V3
- Rename MTCA.4 backplane connectors to follow the MTCA standard
- Change pushbuttons to smaller ones
- Change ARM debug pinhead to IDC with key

fpga_power
- extra wire at GND symbols and pin A1 on IC1M -> junctions
transceivers
- add len match directive for calibration resistor (UG476, p303)
gtx_data_splitter
- IC25, pin 5 extra wire -> junction
regulators
- LDOs have max dropout 400mV. Safer/more robust then to provide P1V5 and P3V8 instead of P1V4 and P3V7.
- T1, T3: INH/UVLO is connected through internal resistor divider to AGND. Should they (T1 and T3) also be connected to AGND ?
pll
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
clk_external
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
  - Diodes on TR3 secondary need refdes
sfp
- J3, J4, pins 9 and 31 extra wire -> junction

IC5: The CLK_HELPER_VCXO come in a capa that is pushed to P3V3A before go to XIN. Is that normal ? Or It's a mistake and only CE Have to be push to P3V3A ?
AGND / GND of LMZ31704: Do you need a single net connect between AGND and GND or no connect between ?. I don't really understand your comment. Tom: there's no need for the net tie as AGND and GND are connected inside the chip.
GTX Differential Pair. Could you review The “Transceivers” Page ? It is normal that for exemple “LINK0_GTX_TX_FB_P/N” goes not in BGA but “LINK0_GTX_TX_P” goes on 2 different Pair of BGA ?
If we search “UNIV_ID_SDA” or SCL. We found that there is 2 with the same net name but not connected together. (Page “Management” and Page “FPGA_local_peripherals”). Should be connect all together. Or it is right ?
Tom: these buses are separate, we could rename them to make this clear.

Ertm14 schematics & layout review