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# Simple PXI express FMC Carrier Board (SPEXI)
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## Project description
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The PXI express FMC Carrier Board (SPEXI) is the PXI express version of
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the [SPEC board](https://www.ohwr.org/project/spec). It is an FMC
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carrier that can hold one FMC card and an SFP connector. On the PXI
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express side it has a 4-lane interface, while the FMC mezzanine slot
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uses a low-pin count connector. This board will be usable with most of
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the FMC cards designed within CERN’s OHR project (e.g. ADC cards, Fine
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Delay).
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LabVIEW drivers are available for the [FMC DEL 1ns 4cha
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delay](https://www.ohwr.org/project/fmc-delay-1ns-8cha/wiki) and [FMC
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TDC 1ns 5cha](https://www.ohwr.org/project/fmc-tdc/wiki) TDC
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mezzanine cards.
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*Spexi* means *"I observe, watch, look at."* in
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Latin.
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*SPEXI v1 production**
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## Main Features
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- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
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anymore*
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- 1x Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)
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- FMC slot with low pin count (LPC) connector
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- Vadj fixed to 2.5V
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- Simple clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs
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Si570)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
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- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
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configuration, Fout=125MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
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- On board memory
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- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16JT-125)
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- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware or of critical data
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(M25P128-VMF6G)
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- Miscellaneous
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- on-board thermometer IC (DS18B20U+)
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- unique 64-bit identifier (DS18B20U+)
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- Front panel containing
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- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
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transceiver ([WhiteRabbit
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support](https://www.ohwr.org/project/white-rabbit)). 1.25 and
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2.5 Gbps.
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- Programmable Red and Green LEDs
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- FMC front panel
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- Internal connectors
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- 1x JTAG header for Xilinx programming during debugging
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- 1x mini USB AB (USB-UART bridge)
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- FPGA configuration. The FPGA can optionally be programmed from:
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- GN4124 SPRIO interface (loaded by software driver at startup)
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- JTAG header
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- SPI 32Mbit flash PROM
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- selectable by GN4124 GPIO. Default option would be loading via
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the SPI flash PROM (stand-alone applications).
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- Debugging features
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Optimised for cost
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- 8-layer PCB
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## PXIe specific features
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\* PXI express form factor, 3U high, single slot
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\* Clock and synchronisation back plane signals
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>PXI clock and synchronisation signals</strong></td>
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<td><strong>PXI express clock and synchronisation signals</strong></td>
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</tr>
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<tr class="even">
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<td>PXI_TRIG[0:7]</td>
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<td>PXIe_DSTARA</td>
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</tr>
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<tr class="odd">
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<td>PXI_CLK10</td>
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<td>PXIe_DSTARB</td>
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</tr>
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<tr class="even">
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<td>PXI_STAR</td>
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<td>PXIe_DSTARC</td>
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</tr>
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<tr class="odd">
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<td>PXI_LBL6</td>
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<td>PXIe_CLK100</td>
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</tr>
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<tr class="even">
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<td>PXI_LBR6</td>
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<td>PXIe_SYNC100</td>
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</tr>
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</tbody>
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</table>
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-----
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## Project information
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- Official production documentation: [EDMS
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EDA-02839](http://edms.cern.ch/nav/EDA-02839/)
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- [CERN specific information](CERN)
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- [Design Information](DesignInfo)
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- [Software](Software)
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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Since the SPEXI is a board which is based on the design of the
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[SPEC](https://www.ohwr.org/project/spec/wiki), some of the
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documentation of the SPEC can also be used.
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- [Getting Started with the
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SPEC](https://www.ohwr.org/project/spec-getting-started/wiki)
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(project)
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- [SPEC Frequently Asked
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Questions](https://www.ohwr.org/project/spec/wikis/FAQ)
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-----
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## Releases
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### Hardware
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- Official production documentation: [EDMS
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EDA-02839](http://edms.cern.ch/nav/EDA-02839/)
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- Pre-release design documentation:
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[SPEXI-V1.0.zip](https://www.ohwr.org/project/spexi/uploads/dd19b51611639085e51bd8c332f305e4/SPEXI-V1-0.zip)
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### FPGA examples (including the .ucf-file)
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- [spexi\_simpledemo.zip](https://www.ohwr.org/project/spexi/uploads/aae580fa08bec2ca351fbf70d323f802/spexi_simpledemo.zip)
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The file **spexi\_simpledemo.zip** contains a demo design and all
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the files including the .bit and .msc files which can be used to
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download this design to the SPEXI using Xilinx iMPACT and the
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download cable, or use the download path via the Gennum GN4124. This
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design contains the interface to the Gennum GN4124, an I2C master to
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access the FMC board eeprom, a carrier control and status register
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to get some information of the SPEXI carrier, and a GPIO register to
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access the four LEDs and the two buttons.
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To download the .mcs file into the SPI memory (M25P128) you will
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need to configure iMPACT to access the SPI flash memory connector to
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the Spartan-6
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150T.
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<!-- end list -->
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- [spexi\_golden.zip](https://www.ohwr.org/project/spexi/uploads/49147527317a03356b8fc9e0a1b9db55/spexi_golden.zip)
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The file **spexi\_golden.zip** contains the same design as
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**spexi\_simpledemo.zip** but does not contain the GPIO register for
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the LEDs and buttons. This design is used to be able to get the
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first information from the SPEXI and the FMC to be able to determine
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which other FMC specific FPGA design could be loaded
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safely.
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<!-- end list -->
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- [spexi\_pts.zip](https://www.ohwr.org/project/spexi/uploads/748fbd2f4a56afbba23ddd48e6c7ed39/spexi_pts.zip)
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The file **spexi\_pts.zip** contains the complete set of VHDL/FPGA
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designs and corresponding phyton files for the [Production Test
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Suite](https://www.ohwr.org/project/pts). This PTS is used to test
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the boards functionally after manufacturing. Because of this the
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designs also contain several examples of how to connect to the other
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interfaces on the SPEXI carrier.
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-----
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## Contacts
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### Commercial producers
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- [SPEXI](http://www.incaacomputers.com/products/spexi/) [INCAA
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Computers](http://incaacomputers.nl), Netherlands.
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### General question about project
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- [Adriaan Rijllart](mailto:Adriaan.Rijllart@cern.ch) - CERN - project
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initiator
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>06-04-2011</td>
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<td>First ideas for project.</td>
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</tr>
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<tr class="odd">
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<td>17-01-2012</td>
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<td>Price Enquiry sent out for design by industry based on [SPEC board](https://www.ohwr.org/project/spec/wiki).</td>
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</tr>
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<tr class="even">
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<td>12-03-2012</td>
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<td>Order for design and two pre-series boards placed with INCAA. Delivery by 12-07-2012.</td>
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</tr>
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<tr class="odd">
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<td>16-05-2012</td>
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<td>Schematics being made.</td>
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</tr>
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<tr class="even">
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<td>29-05-2012</td>
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<td>Removed SATA connectors and stand-alone possibility from specification.</td>
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</tr>
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<tr class="odd">
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<td>17-08-2012</td>
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<td>V0 Schematics and PCB uploaded and available for review</td>
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</tr>
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<tr class="even">
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<td>30-08-2012</td>
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<td>First review V0 [Review20120830](Review20120830).</td>
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</tr>
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<tr class="odd">
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<td>04-10-2012</td>
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<td>Second schematics review V0.</td>
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</tr>
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<tr class="even">
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<td>19-11-2012</td>
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<td>V0-2 ready for review.</td>
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</tr>
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<tr class="odd">
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<td>07-11-2012</td>
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<td>V0-2 reviewed. Only one single minor comment.</td>
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</tr>
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<tr class="even">
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<td>21-01-2013</td>
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<td>Bare PCBs ready for assembly of components.</td>
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</tr>
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<tr class="odd">
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<td>07-02-2013</td>
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<td>PCBs should be assembled by 22 February 2013.</td>
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</tr>
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<tr class="even">
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<td>07-03-2013</td>
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<td>Assembled PCB available. Production Test Software being written based on SVEC PTS.</td>
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</tr>
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<tr class="odd">
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<td>28-06-2013</td>
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<td>V1-0 files being finalised. Ready in a week.</td>
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</tr>
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<tr class="even">
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<td>02-07-2013</td>
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<td>V1-0 files ready for verification and cleanup by CERN design office.</td>
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</tr>
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<tr class="odd">
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<td>30-07-2013</td>
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<td>V1-0 files reviewed. Main comments about component spacing. Will clean up design.</td>
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</tr>
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<tr class="even">
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<td>28-08-2013</td>
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<td>Added PROM to design and cleaned up files. Will be checked by CERN design office. Ordered 10 boards.</td>
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</tr>
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<tr class="odd">
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<td>03-09-2012</td>
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<td>Prototype SPEXI board received (from base layout).</td>
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</tr>
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<tr class="even">
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<td>25-09-2013</td>
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<td>Design V1-0 checked and improved. Released for production.</td>
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</tr>
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<tr class="odd">
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<td>08-10-2013</td>
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<td>Driver Fine Delay card ported from SPEC to SPEXI. Ready for testing. TDC driver will be ported next.</td>
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</tr>
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<tr class="even">
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<td>03-12-2013</td>
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<td>Labview Driver available for <a href="https://www.ohwr.org/project/fmc-delay-1ns-8cha/wiki">FMC DEL 1ns 4cha</a> and [FMC TDC 1ns 5cha](https://www.ohwr.org/project/fmc-tdc/wiki).</td>
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</tr>
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<tr class="odd">
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<td>30-01-2014</td>
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<td>Series production of 10 cards received at CERN.</td>
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</tr>
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<tr class="even">
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<td>30-04-2014</td>
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<td>Ordered 25 boards.</td>
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</tr>
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<tr class="odd">
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<td>04-06-2014</td>
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<td>Airbus Defence&Space: Evaluating SPEXI for use as backbone for future test systems for space electronics.</td>
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</tr>
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<tr class="even">
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<td>23-07-2014</td>
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<td>Astrium GmbH, Germany, will use the SPEXI with the <a href="https://www.ohwr.org/project/fmc-adc-2k24b8cha/wiki">24 bit ADC</a> for measurements using PT1000.</td>
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</tr>
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<tr class="odd">
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<td>31-07-2014</td>
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<td>Received the 25 boards.</td>
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</tr>
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<tr class="even">
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<td>04-09-2015</td>
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<td>4 SPEXI boards with FMC-DEL cards have been deployed in the kicker control systems at CERN (LEIR and others).</td>
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</tr>
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<tr class="odd">
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<td>08-09-2015</td>
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<td>A SPEXI boards with a FMC-TDC card is under study to be used.</td>
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</tr>
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<tr class="even">
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<td>22-04-2016</td>
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<td>Airbus Defence&Space is using the SPEXI as their backbone in test systems for space electronics.</td>
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</tr>
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<tr class="odd">
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<td>03-10-2016</td>
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<td>The Ecole d'Ingénieurs in Fribourg will use the SPEXI</td>
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</tr>
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<tr class="even">
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<td>29-03-2017</td>
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<td>In SM18 the SPEXI will be used with a TDC for magnet quench trigger time stamping</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij, Adriaan Rijllart - 31 March 2017
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