... | ... | @@ -47,10 +47,12 @@ complex modules. |
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- Use registers in IOB for in/out to get well-defined timing,
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independent of routing
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- Check crossings of clock domains, use synchronizer stages when
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needed
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needed (e.g. gc\_sync\_ffs in modules/common of
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[general-cores](https://www.ohwr.org/project/general-cores))
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- Replace deep if-then statements by state machine
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- Resets synchronized: use as on data input of registers
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- State machine recover from illegal states
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- State machine recover from illegal states, i.e. always define the
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"others" state, preferably to go to IDLE state of your state
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machine, if happens.
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- Follow the naming convention from the
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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that
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