... | @@ -57,12 +57,10 @@ complex modules. |
... | @@ -57,12 +57,10 @@ complex modules. |
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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that
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that
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- the inputs/outputs signals in your module(s) finish with
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- the inputs/outputs signals in your module(s) finish with
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\_i/\_o, and bidirectional with \_b,
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\_i/\_o, bidirectional with \_b, asynchronous signals have \_a
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- asynchronous signals should have *a* before \_i/\_o/\_b in
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before \_i/\_o/\_b in their names, and pulses have *pX* in their
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their names
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names(where X is the width of the pulse, e.g. single-cycle pulse
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- signals that are pulses, should have *pX* in their names,
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should have \_p1 in its name)
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where X is the width of the pulse, e.g. single-cycle pulse
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should have \_p1 in its name
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- do not end names of the signals in your modules with *i/\_o/\_b
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- do not end names of the signals in your modules with *i/\_o/\_b
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and do not begin signal names with s* (the optional naming
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and do not begin signal names with s* (the optional naming
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convention from the guidelines that is not recommended)
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convention from the guidelines that is not recommended)
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