... | @@ -56,9 +56,8 @@ complex modules. |
... | @@ -56,9 +56,8 @@ complex modules. |
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- Follow the naming convention from the
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- Follow the naming convention from the
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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that
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that
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- the inputs/outputs signals in your module(s) are followed:
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- the inputs/outputs signals in your module(s) finish with
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- input signal should finish with \_i, output with \_o,
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\_i/\_o, and bidirectional with \_b,
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bidirectional with \_b
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- asynchronous signals should have *a* before \_i/\_o/\_b in
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- asynchronous signals should have *a* before \_i/\_o/\_b in
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their names
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their names
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- signals that are pulses, should have *pX* in their names,
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- signals that are pulses, should have *pX* in their names,
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