... | @@ -51,19 +51,29 @@ complex modules. |
... | @@ -51,19 +51,29 @@ complex modules. |
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- Replace deep if-then statements by state machine
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- Replace deep if-then statements by state machine
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- Resets synchronized: use as on data input of registers
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- Resets synchronized: use as on data input of registers
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- State machine recover from illegal states
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- State machine recover from illegal states
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- at minimum, check that the following naming conventions of
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- Follow the naming convention from the
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inputs/outputs signals in your module(s) are followed:
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[guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines), at minimum check
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- input signal should finish with \_i, output with \_o,
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that
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bidirectional with \_b
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- the inputs/outputs signals in your module(s) are followed:
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- asynchronous signals should have *a* before \_i/\_o/\_b in their
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- input signal should finish with \_i, output with \_o,
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names
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bidirectional with \_b
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- signals that are pulses, should have *pX* in their names, where
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- asynchronous signals should have *a* before \_i/\_o/\_b in
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X is the width of the pulse, e.g. single-cycle pulse should have
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their names
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*p1* in its name
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- signals that are pulses, should have *pX* in their names,
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where X is the width of the pulse, e.g. single-cycle pulse
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should have \_p1 in its name
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- do not end names of the signals in your modules with *i/\_o/\_b
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and do not begin signal names with s* (the optional naming
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convention from the guidelines that is not recommended)
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- examples of non-clear code
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- examples of non-clear code
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- if your code is auto-generated (e.g. by wbgen2) do not modify it
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- if your code is auto-generated (e.g. by wbgen2) do not modify it
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unless you are really sure what you do (usually, this never happens)
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unless you are really sure what you do (usually, this never happens)
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- State copyright and license in all files, see example
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- State copyright and license in all files, [see
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example](https://www.ohwr.org/4734)
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- Git:
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- don't commit Modelsim <sub>transcript</sub>
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- don't commit the <sub>.xise</sub> in <sub>syn/</sub> unless it's
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in a release commit
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- Set a signal, use value on line afterwards (takes 'previous'
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- Set a signal, use value on line afterwards (takes 'previous'
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value). Behavior would be different if it was a variable
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value). Behavior would be different if it was a variable
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