... | @@ -62,6 +62,15 @@ receive from reviewers) |
... | @@ -62,6 +62,15 @@ receive from reviewers) |
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- Check crossings of clock domains, use synchronizer stages when
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- Check crossings of clock domains, use synchronizer stages when
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needed (e.g. gc\_sync\_ffs in modules/common of
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needed (e.g. gc\_sync\_ffs in modules/common of
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[general-cores](https://www.ohwr.org/project/general-cores))
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[general-cores](https://www.ohwr.org/project/general-cores))
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- Before using an asynchronous input signal (e.g. from DIO) in your
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synchronous design, first synchronise it with your clock domain and
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then deglitch the signal, preferably use
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gc\_async\_signals\_input\_stage in modules/common of
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[general-cores](https://www.ohwr.org/project/general-cores)
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- Make sure that a synchronised signal is used only in processes that
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use the same clock as the one the signal is synchronised to.
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- Use only real clocks as clocks for registers. Do not use a
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combinatorial or generated signal as a clock for a register
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- Replace deep if-then statements by state machine
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- Replace deep if-then statements by state machine
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- Initialize in reset all signals for which you assign value in a
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- Initialize in reset all signals for which you assign value in a
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process
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process
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... | @@ -89,17 +98,12 @@ receive from reviewers) |
... | @@ -89,17 +98,12 @@ receive from reviewers) |
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very fast and the name will mean nothing)
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very fast and the name will mean nothing)
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- Check whether any module or function that you need in your design
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- Check whether any module or function that you need in your design
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and that is not specific to your project (say, it deals with
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and that is not specific to your project (say, it deals with
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Endianness or calculate CRC) exists already in
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Endianness or calculates a CRC) exists already in
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[general-cores](https://www.ohwr.org/project/general-cores),
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[general-cores](https://www.ohwr.org/project/general-cores),
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[wr-cores](https://www.ohwr.org/project/wr-cores), or opencores.org:
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[wr-cores](https://www.ohwr.org/project/wr-cores), or opencores.org:
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- if it does not exist, consider adding it there
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- if it does not exist, consider adding it there
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- if it does exist already, consider reusing and extending/fixing
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- if it does exist already, consider reusing and extending/fixing
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if needed
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if needed
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- Before using an asynchronous input signal (e.g. from DIO) in your
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synchronous design, first synchronise it with your clock domain and
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then deglitch the signal, preferably use
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gc\_async\_signals\_input\_stage in modules/common of
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[general-cores](https://www.ohwr.org/project/general-cores)
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- If your code is auto-generated (e.g. by wbgen2) do not modify it,
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- If your code is auto-generated (e.g. by wbgen2) do not modify it,
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unless you are really sure what you do (usually you need to do the
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unless you are really sure what you do (usually you need to do the
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modification because you don't know)
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modification because you don't know)
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... | @@ -191,5 +195,5 @@ at CERN, I think they are still valid and useful. |
... | @@ -191,5 +195,5 @@ at CERN, I think they are still valid and useful. |
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-----
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-----
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Erik van der Bij, Maciej Lipinski - 15 January 2018
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Erik van der Bij, Maciej Lipinski - 26 September 2018
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