... | @@ -78,12 +78,15 @@ receive from reviewers) |
... | @@ -78,12 +78,15 @@ receive from reviewers) |
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reset is not in sensitivity list)
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reset is not in sensitivity list)
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- Do not use "new" and "old" in the names (the new will become old
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- Do not use "new" and "old" in the names (the new will become old
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very fast and the name will mean nothing)
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very fast and the name will mean nothing)
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- Check whether the module or function that you want to develop and
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- Check whether any module or function you need in your design and
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that is not specific to your project (say, it deals with Endianess
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that is not specific to your project (say, it deals with Endianness
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or calculate CRC) exists already in
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or calculate CRC) exists already in
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[general-cores](https://www.ohwr.org/project/general-cores) or
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[general-cores](https://www.ohwr.org/project/general-cores),
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[wr-cores](https://www.ohwr.org/project/wr-cores)
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[wr-cores](https://www.ohwr.org/project/wr-cores), or opencores.org:
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- Before using a asynchronous input signal (e.g. from DIO) in your
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- if it does not exist, consider adding it there
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- if it does exist already, consider reusing and extending/fixing
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if needed
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- Before using an asynchronous input signal (e.g. from DIO) in your
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synchronous design, first synchronise it with your clock domain and
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synchronous design, first synchronise it with your clock domain and
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then deglitch the signal, preferably use
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then deglitch the signal, preferably use
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gc\_async\_signals\_input\_stage in modules/common of
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gc\_async\_signals\_input\_stage in modules/common of
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