... | @@ -14,6 +14,10 @@ |
... | @@ -14,6 +14,10 @@ |
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- VHDL for logic synthesis, Rushton ([CERN
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- VHDL for logic synthesis, Rushton ([CERN
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Library](https://cds.cern.ch/record/1418914?ln=en), [older
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Library](https://cds.cern.ch/record/1418914?ln=en), [older
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edition](https://cds.cern.ch/record/362370?ln=en"))
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edition](https://cds.cern.ch/record/362370?ln=en"))
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- Formal Verification: An Essential Toolkit for Modern VLSI Design, Oreilly
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https://www.oreilly.com/library/view/formal-verification/9780128008157/
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*Soon available in the CERN library (24/08/2021)*
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... | @@ -195,5 +199,5 @@ at CERN, I think they are still valid and useful. |
... | @@ -195,5 +199,5 @@ at CERN, I think they are still valid and useful. |
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Erik van der Bij, Maciej Lipinski - 6 May 2020
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Erik van der Bij, Maciej Lipinski - 24 August 2021
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