... | @@ -64,8 +64,9 @@ complex modules. |
... | @@ -64,8 +64,9 @@ complex modules. |
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- the names of the signals inside your module(s) do not finish
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- the names of the signals inside your module(s) do not finish
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with "\_i"/"\_o"/"*b" and do not begin with "s*" (the optional
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with "\_i"/"\_o"/"*b" and do not begin with "s*" (the optional
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naming convention from the guidelines that is not recommended)
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naming convention from the guidelines that is not recommended)
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- whenever it is known/fixed, indicate the clock frequency in its
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- the names of clock signals, whenever it is known/fixed, indicate
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name, i.e.: clk\_125m\_pllref, clk\_80m\_ADC, clk\_20m\_vcxo\_i
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the frequency, e.g..: clk\_125m\_pllref, clk\_80m\_ADC,
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clk\_20m\_vcxo\_i
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- make sure that only needed signals are in sensitivity list of a
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- make sure that only needed signals are in sensitivity list of a
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process (e.g. if you use process with synchronous reset, make sure
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process (e.g. if you use process with synchronous reset, make sure
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reset is not in sensitivity list)
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reset is not in sensitivity list)
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