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# Schematics design review checklist
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-----
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## Create and study BOM, powerlist and netlist
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1. **Use as few different components as possible**.
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- A single BOM line is costing roughly 100-200 CHF (ordering,
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putting roll on machine etc.) and you will save time for
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yourself (checking BOM, ordering) and will also have less
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chances of mounting the wrong components.
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- **Print the BOM**, check the resistor values used and see if you
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can remove some values by putting them in parallel or series (or
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actually taking existing values that are as good). The same for
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capacitors.
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- Check if high precision or high power components are used (e.g.
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0.1% or 0.5W) are needed.
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- Avoid through-hole components as they should be manually
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mounted.
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2. Print out the **power and ground list** for all ICs and check if
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they’re correctly connected.
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3. Print out the **netlist**, sort alphabetically and check for any
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inconsistencies (in naming, bus signals all used).
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This takes some time, but really can show non-obvious mistakes.
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4. For any newly created symbols, check the pin numbering.
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- CERN specific: check if only symbols created by the design
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office are used.
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## Study schematics
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1. Buses: check if all bits are used.
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2. Differential signals: check if both \_P and \_N are used (and have
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really this polarity).
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3. Power signals naming: use P3V3, P5V, M12V etc.
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4. Check each connection of ICs. Notably hard-wired settings of ICs
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(division/amplification factors, operating modes etc. Add a note).
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5. Check polarity of capacitors, notably on those connected to negative
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power supplies.
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6. Check correct polarity of diodes and LEDs.
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7. Check if enough decoupling for each IC.
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8. Check global decoupling of power supplies (large cap at point of
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generation or entry).
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9. Check protection circuits on the signals. Verify in detail where
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current flows through.
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10. Check if signal levels are compatible between outputs and inputs
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(LVTTL etc.).
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11. Check for any crosses on wires (showing no connection) and check
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connectivity of crossing wires (a dot should show connected).
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12. Check if there is a note about hard-wired settings of ICs
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(division/amplification factors, operating modes etc.).
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13. Check if components are aligned to make the schematics look clear.
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14. Check consistency of naming and numbering of schematic pages.
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## FMC mezzanine cards
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1. EEPROM: GA1 should connect to A0, GA0 should connect to A1
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(Observation 5.22 [ANSI/VITA 57.1
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spec](http://cdsweb.cern.ch/record/1172409?ln=en) - CERN only).
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2. TDI and TDO are connected together if not used on the mezzanine
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3. Connect all mounting holes to ground (this is not in the
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specification, but is the best practice).
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4. Have a note on the schematic about allowed Vadj level (e.g. most
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carriers on ohwr can provide only 2V5).
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5. Foresee decoupling capacitors near the FMC connector (allowing power
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pins to work as signal return too).
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-----
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Erik van der Bij - 6 November 2015
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