... | @@ -4,41 +4,56 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -4,41 +4,56 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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## Specification
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## Specification
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### FPGA
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Wherever possible, the same components shall be used as in the [DI/OT ZU7 System Board](https://ohwr.org/project/diot-sb-zu/tree/master/hw)
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* **Kintex Ultrascale** - XCKU035-1SFVA784C
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### Components
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#### FPGA
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### FMC
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* **Kintex Ultrascale** - XCKU035-1FFVA1156C
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#### FMC
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* **HPC** with at least 4 MGTs - to e.g. host COTS ADC FMCs, requires 160 FPGA I/Os
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* **HPC** with at least 4 MGTs - to e.g. host COTS ADC FMCs, requires 160 FPGA I/Os
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* configurable **Vadj** 1.8V 2.5V 3.3V
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* **Vadj** 1.8V enabled/disabled by FPGA pin
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### Connectivity
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#### Connectivity
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* front-panel, ideally includes
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* front-panel, ideally includes
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- 1 or 2 LEDs
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- 1 or 2 LEDs
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- a DIO with lemo-00
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- a DIO with lemo-00
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### Memories
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#### Memories
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* DDR3 SO-DIMM slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* **DDR4 SO-DIMM** slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* QSPI Flash - for FPGA bitstream, size depending on chosen FPGA
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* **QSPI Flash** - for FPGA bitstream
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* (DDR4: **MT40A512M16LY-075:E** (x2) - DDR4 not supported by series-7)
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* **24AA025E48-I/SN** EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board (see [details on Peripheral Boards identification](https://ohwr.org/project/diot/wikis/crate_monitoring) )
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* **24AA025E48-I/SN** EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board
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### Power
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#### Power
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* IRPS5401 PMIC
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* IRPS5401 PMIC
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* separate PMIC for Vadj generation (also fed to FPGA I/O banks connected to FMC)
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* separate DC/DC for Vadj generation; its *enable* input shall be controlled by FPGA. The same Vadj shall power FPGA I/O banks that are connected to FMC I/Os so that Vadj can be turned on ONLY when FMC mezzanine supported voltages match carrier supported voltage (1.8V).
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### Miscellaneous
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#### Miscellaneous
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* Xilinx JTAG connector: **MOLEX 87832-1420**
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* Xilinx JTAG connector: **MOLEX 87832-1420**
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* Thermometers
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* Thermometers
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* LEDs in the front panel
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* LEDs in the front panel
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### Mechanical
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#### Mechanical
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* 100mm x 220mm
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* 100mm x 220mm
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* **P1** and (optionally) **P6** backplane connectors
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* **P1** and **P6** backplane connectors
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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### Requirements
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* The board shall have EEPROM-based identification mechanism implemented according to [Peripheral Boards identification procedure](https://ohwr.org/project/diot/wikis/crate_monitoring#peripheral-boards-identification)
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* the same SERVMOD_N signal shall drive:
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- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
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- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
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* Backplane P1 connector pins shall have dual IO/JTAG function (selectable with SERVMOD_N):
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- *A3* - TDI
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- *D3* - TDO
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- *B4* - TMS
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- *H4* - TCK
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- *K4* - nTRST
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* MGT backplane lanes (P1.A5,A6,D5,E5) shall be connected to FPGA MGT
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### To be defined:
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### To be defined:
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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- A TE/ABT: JTAG to backplane please |
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- A TE/ABT: JTAG to backplane please |