... | @@ -11,7 +11,10 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -11,7 +11,10 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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### FMC
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### FMC
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* **HPC** (?) - requires 160 FPGA I/Os
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* **HPC** (?) - requires 160 FPGA I/Os
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* configurable **Vadj** (Artix-7 I/Os 1.2V - 3.3V)
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### Miscellaneous
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*
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### Mechanical
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### Mechanical
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... | @@ -19,3 +22,6 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -19,3 +22,6 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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* **P1** and (optionally) **P6** backplane connectors
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* **P1** and (optionally) **P6** backplane connectors
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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### To be defined:
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* remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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* identification of the board over I2C (EEPROM + Id?) |