... | @@ -22,6 +22,7 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -22,6 +22,7 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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* DDR3 SO-DIMM slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* DDR3 SO-DIMM slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* QSPI Flash - for FPGA bitstream, size depending on chosen FPGA
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* QSPI Flash - for FPGA bitstream, size depending on chosen FPGA
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* (DDR4: **MT40A512M16LY-075:E** (x2) - DDR4 not supported by series-7)
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* (DDR4: **MT40A512M16LY-075:E** (x2) - DDR4 not supported by series-7)
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* EEPROM with unique ID attached to backplane I2C and GA0..2 - **24AA025UID**
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### Power
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### Power
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* IRPS5401 PMIC
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* IRPS5401 PMIC
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... | @@ -41,4 +42,3 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -41,4 +42,3 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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### To be defined:
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### To be defined:
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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- A TE/ABT: JTAG to backplane please |
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- A TE/ABT: JTAG to backplane please |
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* identification of the board over I2C (EEPROM + Id?) |
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