... | @@ -38,7 +38,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
... | @@ -38,7 +38,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
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* *SHARED_BUS0..4* connected to FPGA I/Os
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* *SHARED_BUS0..4* connected to FPGA I/Os
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* *RST_N* connected to FPGA I/O
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* *RST_N* connected to FPGA I/O
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* *SYSEN_N* connected to FPGA I/O
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* *SYSEN_N* connected to FPGA I/O
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* *CLK_P/CLK_N* connected to clock-capable FPGA I/O
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* *CLK_P/CLK_N* connected to Si5341
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* **P6**:
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* **P6**:
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* LVDS lanes (*DIFF11..14*) connected to FPGA I/Os
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* LVDS lanes (*DIFF11..14*) connected to FPGA I/Os
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* **P4** populated depending on FPGA I/Os availability:
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* **P4** populated depending on FPGA I/Os availability:
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... | @@ -59,6 +59,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
... | @@ -59,6 +59,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
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#### Clock generation
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#### Clock generation
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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* operating in zero delay mode (external feedback loop from *out9* to *fb_in*)
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* operating in zero delay mode (external feedback loop from *out9* to *fb_in*)
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* local oscillator or CLK_P/N from DI/OT backplane as possible clock inputs
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* optional DRTIO oscillators
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* optional DRTIO oscillators
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#### Power
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#### Power
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