... | ... | @@ -58,6 +58,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
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#### Clock generation
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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* operating in zero delay mode (external feedback loop from *out9* to *fb_in*)
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* optional DRTIO oscillators
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#### Power
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