... | @@ -10,8 +10,13 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -10,8 +10,13 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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### FMC
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### FMC
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* **HPC/LPC** (?) - requires 160 FPGA I/Os
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* **HPC preferred e.g. for COTS ADC cards (LPC fallback)** (?) - requires 160 FPGA I/Os
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* configurable **Vadj** 1.8V 2.5V 3.3V
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* configurable **Vadj** 1.8V 2.5V (3.3V)
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### Connectivity
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* front-panel, ideally includes
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- 1 or 2 LEDs
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- a DIO with lemo-00
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### Memories
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### Memories
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* DDR4: **MT40A512M16LY-075:E** (x2) - the same as DI/OT System Board
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* DDR4: **MT40A512M16LY-075:E** (x2) - the same as DI/OT System Board
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... | @@ -33,5 +38,6 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
... | @@ -33,5 +38,6 @@ This page gathers the design specification of the FMC carrier Peripheral Board f |
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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### To be defined:
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### To be defined:
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* remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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- A TE/ABT: JTAG to backplane please
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* identification of the board over I2C (EEPROM + Id?) |
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* identification of the board over I2C (EEPROM + Id?) |