... | ... | @@ -44,14 +44,14 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
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### Requirements
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* The board shall have EEPROM-based identification mechanism implemented according to [Peripheral Boards identification procedure](https://ohwr.org/project/diot/wikis/crate_monitoring#peripheral-boards-identification)
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* the same SERVMOD_N signal shall drive:
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- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
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- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
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- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
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- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
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* Backplane P1 connector pins shall have dual IO/JTAG function (selectable with SERVMOD_N):
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- *A3* - TDI
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- *D3* - TDO
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- *B4* - TMS
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- *H4* - TCK
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- *K4* - nTRST
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- *A3* - TDI
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- *D3* - TDO
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- *B4* - TMS
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- *H4* - TCK
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- *K4* - nTRST
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* MGT backplane lanes (P1.A5,A6,D5,E5) shall be connected to FPGA MGT
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### To be defined:
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