... | @@ -54,7 +54,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
... | @@ -54,7 +54,7 @@ Wherever possible, the same components shall be used as in the [DI/OT ZU7 System |
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* **DDR4 SO-DIMM** slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* **DDR4 SO-DIMM** slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* **QSPI Flash** - for FPGA bitstream
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* **QSPI Flash** - for FPGA bitstream
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* **24AA025E48-I/SN** EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board (see [details on Peripheral Boards identification](https://ohwr.org/project/diot/wikis/crate_monitoring) )
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* **24AA025E48-I/SN** EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board (see [details on Peripheral Boards identification](https://ohwr.org/project/diot/wikis/crate_monitoring) )
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* optional microSD card slot (?)
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* [optional] eMMC / microSD card slot - if spare FPGA pins are available
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#### Clock generation
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#### Clock generation
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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