[fpga-bank-87-88] get rid of IC37 by rearranging I/Os
We can get rid of IC37 by rearranging I/Os, it's also desired to simplify access to some of them from the FPGA. In total there are 18 free I/Os spread among banks 27, 28, 66, 67, 68 (all 1.8V):
- move I2C_SCL, I2C_SDA, I2C_SW_RST# to bank 68; and use low-voltage I2C mux (i2c_mux.SchDoc) powered from 1.8V that accepts pull-ups to 3.3V on secondary side or use PCA9306DCUR like in the original PXIe design to translave 1.8V to 3.3V I2C.
- move CPCIS_I2C_SCL, CPCIS_I2C_SDA to bank 28; use voltage translating I2C transceiver to convert 1.8V - 3.3V
- move Helper_DCXO_SCL, Helper_DCXO_SDA, Main_DCXO_SCL, Main_DCXO_SDA, DCXO_OE to bank 28; no translation required, OSC7 and OSC8 (CLK_buffer_DRTIO_CDR.SchDoc) are already 1.8V powered with 1.8V pull-ups on I2C interface.
- move UART-PL_RXD, UART-PL_TXD to bank 66; then in fpga-ps-mio.SchDoc move UART_TXD/UART_RXD to MIO54, MIO55; in user_interface.SchDoc change VIO of IC3 to 1.8V
- move FMC_PRSNT to PS MIO
- remove FMC_PG_M2C - it is part of HPC FMC, we have only LPC FMC
- move all the remaining I/Os connected to IC37 (RST#, PRST#, PWR_FAIL#, FMC_PG_C2M, SFP_RSSI, PWRBTN#, F_IO0, F_IO1, P_PRES0, P_PRES1, F_RST, P_RST) to Banks 87/88 - pins are freed in the steps described above.
- remove IC37 and EXT_INT1 signal
- connect EXT_INT0 to INTA port of IC41.