... | ... | @@ -66,16 +66,12 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| Mounting holes for FPGA heatsink | | | |
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| USB UART | | 1 | | |
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### Compact PCI Serial backplane connectors
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* 287 FPGA I/Os in total
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* 8 MGTs (1 MGT per slot)
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### LPC FMC slot with 4 MGTs
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* 68 user-defined I/Os (34 diff-pairs)
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* Voltage translators - Ultrascale has 48 HD I/Os (3.3V max) and 416 HP I/Os (1.8V max)
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* I2C SCL and SDA
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* Present signal
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* 1 LPC MGTs
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* 1 LPC MGT
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* 3 HPC MGTs (required for FRAS, EN-SMM)
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* Vadj configurable?: 1.8V, 2.5V, 3.3V for LPC pins
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... | ... | @@ -90,6 +86,25 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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* ESD strips on both sides of the board, along the bottom edge of the PCB with discharge resistors according to section 3.5.10 of CPCI-S.0 specification.
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* The length of ESD strip segment 2 shall be 115mm.
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### Compact PCI Serial backplane connectors
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* 287 FPGA I/Os in total
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* 8 MGTs (1 MGT per slot)
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* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
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* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
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* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
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* PRST# (P1.H2) - left open (there is no reset button in DI/OT crate)
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* PWRBTN# (P1.C3) - left open (there is no ACPI power button in DI/OT crate, according to CPCI-S.0 (REQ 4.41) the support of this signal is optional)
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### ZU7 HD (3.3V) and HP (1.8V) I/O planning
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| **I/O connector** | **I/O name** | **I/O index** | **No of pins** | **ZU7 I/O bank type** |
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| ------ | ------ | ------ | ------ | ------ |
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| CPCIs backplane | I2C | *P1.B2*, *P1.C2* | 2 | HD |
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| CPCIs backplane | RST# | *P1.F2* | 1 | HD |
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| CPCIs backplane | PWRFAIL# | *P1.F2* | 1 | HD |
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| CPCIs backplane | WAKE_IN# | *P1.I2* | 1 | HD |
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| CPCIs backplane | Monitoring I/Os | | 11 | HD |
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## Related links and documents
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## Contacts
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