... | ... | @@ -30,10 +30,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) |
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| Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
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| Helper OSC | LF VCXO026156 | 1 | SPEC, AFCK | 20 MHz |
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| Clock generator | CDCM61004RHBT | 1 | SPEC, FASEC, AFCK | 25 MHz -> 125 MHz |
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| | AD9516 | | WRS | 25 MHz -> 125 MHz (and others, can be programmed, to allow also 10G WR?) |
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| Clock generator | AD9516 | | WRS | see clocking scheme below |
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| | Si5341 | | ZCU102, AFCZ | |
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| (optional) Startup OSC | FNETHE025 | 1 | WRS | |
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| Startup OSC | FNETHE025 | 1 | WRS | |
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| I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
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| I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
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| 1-PPS OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal |
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... | ... | @@ -73,6 +72,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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* Present signal
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* 1 LPC MGT
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* 3 HPC MGTs (required for FRAS, EN-SMM)
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* FMC clocks connected to dedicated clocking pins of FPGA I/O banks
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* Vadj and I/Os fixed at 1.8V
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* TODO: compatibility with current CO-HT mezzanines
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... | ... | @@ -97,6 +97,8 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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* PWRBTN# (P1.C3) - left open (there is no ACPI power button in DI/OT crate, according to CPCI-S.0 (REQ 4.41) the support of this signal is optional)
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* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
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### Clocking scheme
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![clk_scheme](uploads/bd3520701b9043e4da1639aea37302be/clk_scheme.png)
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### ZU7 HD (3.3V) and HP (1.8V) I/O planning
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| **I/O connector** | **I/O name** | **I/O index** | **No of pins** | **ZU7 I/O bank type** |
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... | ... | |