... | ... | @@ -10,13 +10,13 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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### SoC / FPGA
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| Zynq Ultrascale+ ZU7 | XCZU7CG-1FFVF1517E | 1 | AFCZ | |
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| Zynq Ultrascale+ ZU7 | XCZU7CG-1FFVF1517E | 1 | [AFCZ](https://github.com/elhep/AFCZ/wiki) | |
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### Memories
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| PS DDR4 8Gb x4 | e.g. MT40A512M16TB | 4 (5 with ECC) | | 8Gb (512M x 16 x 4) |
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| PL DDR4 8Gb | e.g. MT40A512M16TB | 1 | | 8Gb (512M x 16 x 4) |
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| PS DDR4 8Gb x4 | MT40A512M16LY-075:E | 4 (5 with ECC) | | 8Gb (512M x 16 x 4) |
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| PL DDR4 8Gb | MT40A512M16LY-075:E | 1 | | 8Gb (512M x 16 x 4) |
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| QSPI 512Mbit | MT25QU512ABB | 1 | 7S, ZCU102 | NOR Flash |
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| eMMC 32Gb | IS21ES04G-JCLI | 1 | 7S | 4Gb x 8 |
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... | ... | @@ -43,14 +43,28 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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### Other oscillators / clock generators
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| GTH Clk generator/distribution | e.g. Si5341 or AD9516 | 1 | WRS, AFCZ | Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| ?? Clock cross-point switch | IDT 8V54816A | 1 | AFCZ | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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### Power
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| Multi-level solution | e.g. MAX77714 | | | [Maxim power solutions for Xilinx](https://www.maximintegrated.com/en/products/power/switching-regulators/applications/fpga-power/xilinx-fpga-power-solutions/power-solutions-for-xilinx-artix-spartan-and-zynq-fpgas.html/tb_order) |
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| | XR77129ELB-F | | AFCZ | |
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### Miscellaneous
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| 12V, GND headers pads | -- | 1 | -- | For external powering during first tests |
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| Xilinx JTAG connector | -- | 1 | -- | |
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| Self power-cycle circuit driving backplane PS_ON# | | 1 | | In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail |
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| ??? External watchdog chip for PL (or LPD/FPD Watchdogs inside Zynq) | LTC2917HMS-B1#PBF | 1 | FASEC |
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| Thermometers | | 3? | | |
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| (optional) header connector for FPGA fan | | 1 | |
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| Mounting holes for FPGA heatsink | | | |
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| USB UART | | 1 | | |
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## Related links and documents
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... | ... | |