... | ... | @@ -95,8 +95,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
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* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
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* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
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* PRST# (P1.H2) - left open (there is no reset button in DI/OT crate)
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* PWRBTN# (P1.C3) - left open (there is no ACPI power button in DI/OT crate, according to CPCI-S.0 (REQ 4.41) the support of this signal is optional)
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* PRST# (P1.H2) - ESD-protected through I/O buffer / TVS diode
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* PWRBTN# (P1.C3) - ESD-protected through I/O buffer / TVS diode
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* Monitoring I/Os (PS_ON, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through I/O buffer / TVS diode
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* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
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### Clocking scheme
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... | ... | @@ -112,6 +113,8 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| CPCIs backplane | Monitoring I/Os | *P2 rows 7,8* | 11 | HD |
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| CPCIs backplane | Serial GPIO | *P1.G3*, *P1.H3*, *P1.J3*, *P1.K3* | 4 | HD |
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| CPCIs backplane | PCIe presence detect | *P5.A6*, *P5.C5*, *P5.D6*, *P5.F5*, *P5.G6*, *P5.I5*, *P5.J6*, *P5.L5* | 8 | HD |
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| CPCIs backplane | PWRBTN# | *P1.C3* | 1 | HD |
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| CPCIs backplane | PRST# | *P1.H2* | 1 | HD |
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| CPCIs backplane | PCIe/USB/SATA/Eth | * | 288 | HP |
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| FMC connector | User-defined signals | *LA[00..33]_P/N* | 68 | HP |
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