... | ... | @@ -30,8 +30,8 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
|
| DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) |
|
|
|
| Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
|
|
|
| Helper OSC | LF VCXO026156 | 1 | SPEC, AFCK | 20 MHz |
|
|
|
| Clock generator | AD9516 | | WRS | see clocking scheme below |
|
|
|
| | Si5341 | | ZCU102, AFCZ | |
|
|
|
| Clock generator | AD9516 | | WRS | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
|
|
|
| | Si5341 | | ZCU102, AFCZ | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
|
|
|
| Startup OSC | FNETHE025 | 1 | WRS | |
|
|
|
| I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
|
|
|
| I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
|
... | ... | @@ -42,7 +42,6 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
|
### Other oscillators / clock generators
|
|
|
| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
|
|
|
| ------ | ------ | ------ | ------ | ------ |
|
|
|
| GTH Clk generator/distribution | e.g. Si5341 or AD9516 | 1 | WRS, AFCZ | Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
|
|
|
| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
|
|
|
| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
|
|
|
| ?? Clock cross-point switch | IDT 8V54816A | 1 | AFCZ | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
|
... | ... | |