... | ... | @@ -34,8 +34,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
|
| Link/Act LEDs | | 2 | Placed close to SFP cage (probably SMDs on PCB bottom) |
|
|
|
| DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) |
|
|
|
| Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
|
|
|
| Helper OSC | | 1 | | 25 MHz |
|
|
|
| Helper VCXO 25MHz | KV7050B25.0000C3GD00 | 1 | eRTM 14 | or compatible with KV7050B25.0000C3GD00 |
|
|
|
| Helper ext PLL | CDCM61002RHBT | 1 | eRTM14 | Lower jitter than DMTD clock multiplied inside FPGA |
|
|
|
| (optional) Helper programmable OSC | SI549 | 1 | Not mounted for CERN |
|
|
|
| Clock generator | Si5341 | | ZCU102, AFCZ | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
|
|
|
| | <s>AD9516</s> | | WRS | Not enough clock inputs |
|
|
|
| Startup OSC | FNETHE025 | 1 | WRS | |
|
... | ... | |