... | @@ -2,7 +2,7 @@ |
... | @@ -2,7 +2,7 @@ |
|
|
|
|
|
## Project description
|
|
## Project description
|
|
|
|
|
|
The DI/OT System Board is one of the main components of the [Distributed I/O Tier project ecosystem](https://ohwr.org/project/diot/wikis/home). It is mechanically and electrically compliant with the Compact PCI Serial standard (CPCI-S.0).
|
|
The DI/OT System Board is one of the main components of the [Distributed I/O Tier project ecosystem](https://ohwr.org/project/diot/wikis/home). It is mechanically and electrically compliant with the Compact PCI Serial standard (CPCI-S.0). As part of the integration with the [Sinara ecosystem](https://sinara-hw.github.io) for quantum physics experiments, DI/OT System Board will have two executions to serve both CERN and Sinara requirements.
|
|
|
|
|
|
The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using [White Rabbit](https://ohwr.org/project/white-rabbit/wikis/home), Gigabit Ethernet or any other industrial fieldbus.
|
|
The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using [White Rabbit](https://ohwr.org/project/white-rabbit/wikis/home), Gigabit Ethernet or any other industrial fieldbus.
|
|
|
|
|
... | @@ -70,6 +70,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -70,6 +70,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
| FPGA fan control and monitoring | MAX6639AEE+ | | 1 | Provides SMBus interface |
|
|
| FPGA fan control and monitoring | MAX6639AEE+ | | 1 | Provides SMBus interface |
|
|
| Mounting holes for FPGA heatsink | | | |
|
|
| Mounting holes for FPGA heatsink | | | |
|
|
| USB UART | | 1 | | |
|
|
| USB UART | | 1 | | |
|
|
|
|
| Aux clock input | MMCX connector | 1 | | Not mounted on CERN execution of the board. Required by Sinara. |
|
|
|
|
|
|
### LPC FMC slot with 4 MGTs
|
|
### LPC FMC slot with 4 MGTs
|
|
* 68 user-defined I/Os (34 diff-pairs)
|
|
* 68 user-defined I/Os (34 diff-pairs)
|
... | @@ -78,6 +79,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -78,6 +79,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
* Present signal
|
|
* Present signal
|
|
* 1 LPC MGT
|
|
* 1 LPC MGT
|
|
* 3 HPC MGTs (required for FRAS, EN-SMM)
|
|
* 3 HPC MGTs (required for FRAS, EN-SMM)
|
|
|
|
* (optional) more HPC MGTs, to be decided later, depending if it will complicate PCB routing
|
|
* FMC clocks connected to dedicated clocking pins of FPGA I/O banks
|
|
* FMC clocks connected to dedicated clocking pins of FPGA I/O banks
|
|
* Vadj and I/Os fixed at 1.8V
|
|
* Vadj and I/Os fixed at 1.8V
|
|
|
|
|
... | @@ -94,7 +96,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -94,7 +96,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
|
|
|
|
### Compact PCI Serial backplane connectors
|
|
### Compact PCI Serial backplane connectors
|
|
* 287 FPGA I/Os in total
|
|
* 287 FPGA I/Os in total
|
|
* 8 MGTs (1 MGT per slot)
|
|
* 8 MGTs (1 MGT per slot) <br>
|
|
|
|
* In CERN execution of the board, MGT Tx connected through a capacitor to the backplane connector.<br>
|
|
|
|
* As Sinara requires an additional LVDS pair, there will be an option to mount a 0R (L-shaped arrangements of pads with the CAP) instead of the capacitor to connect MGT Tx pair from the backplane to regular PL I/Os.
|
|
* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
|
|
* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
|
|
* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
|
|
* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
|
|
* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
|
|
* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
|
... | @@ -105,7 +109,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -105,7 +109,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
|
* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
|
|
* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
|
|
|
|
|
|
### Clocking scheme
|
|
### Clocking scheme
|
|
![clk_scheme](uploads/bd3520701b9043e4da1639aea37302be/clk_scheme.png)
|
|
![clk_scheme](uploads/f6c80a173b92f6f22405507b4432cbc0/clk_scheme.png)
|
|
|
|
|
|
### ZU7 HD (3.3V) and HP (1.8V) I/O planning
|
|
### ZU7 HD (3.3V) and HP (1.8V) I/O planning
|
|
| **I/O connector** | **I/O name** | **I/O index** | **No of pins** | **ZU7 I/O bank type** |
|
|
| **I/O connector** | **I/O name** | **I/O index** | **No of pins** | **ZU7 I/O bank type** |
|
... | | ... | |