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* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
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* PRST# (P1.H2) - left open (there is no reset button in DI/OT crate)
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* PWRBTN# (P1.C3) - left open (there is no ACPI power button in DI/OT crate, according to CPCI-S.0 (REQ 4.41) the support of this signal is optional)
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* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
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### ZU7 HD (3.3V) and HP (1.8V) I/O planning
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... | ... | @@ -103,7 +104,8 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| CPCIs backplane | RST# | *P1.F2* | 1 | HD |
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| CPCIs backplane | PWRFAIL# | *P1.F2* | 1 | HD |
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| CPCIs backplane | WAKE_IN# | *P1.I2* | 1 | HD |
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| CPCIs backplane | Monitoring I/Os | | 11 | HD |
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| CPCIs backplane | Monitoring I/Os | *P2 rows 7,8* | 11 | HD |
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| CPCIs backplane | Serial GPIO | *P1.G3*, *P1.H3*, *P1.J3*, *P1.K3* | 4 | HD |
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## Related links and documents
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