... | ... | @@ -34,9 +34,10 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| Link/Act LEDs | | 2 | Placed close to SFP cage (probably SMDs on PCB bottom) |
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| DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) |
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| Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
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| Helper OSC | LF VCXO026156 | 1 | SPEC, AFCK | 20 MHz |
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| Clock generator | AD9516 | | WRS | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
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| | Si5341 | | ZCU102, AFCZ | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
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| Helper OSC | | 1 | | 25 MHz |
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| Helper ext PLL | CDCM61002RHBT | 1 | eRTM14 | Lower jitter than DMTD clock multiplied inside FPGA |
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| Clock generator | Si5341 | | ZCU102, AFCZ | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
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| | <s>AD9516</s> | | WRS | Not enough clock inputs |
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| Startup OSC | FNETHE025 | 1 | WRS | |
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| I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
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| I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
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... | ... | @@ -49,8 +50,6 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| ------ | ------ | ------ | ------ | ------ |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| ?? Clock cross-point switch | | 1 | | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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| | | | | Alternatively, input all clocks to FPGA and decide there on crossing/switching. TODO: measure how much jitter adds Ultrascale+ family |
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### Power
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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... | ... | |