... | @@ -47,6 +47,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -47,6 +47,7 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| ?? Clock cross-point switch | IDT 8V54816A | 1 | AFCZ | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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| ?? Clock cross-point switch | IDT 8V54816A | 1 | AFCZ | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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| | | | | Alternatively, input all clocks to FPGA and decide there on crossing/switching. TODO: measure how much jitter adds Ultrascale+ family |
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### Power
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### Power
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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... | | ... | |