... | @@ -10,124 +10,10 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
... | @@ -10,124 +10,10 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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![DIOT-sb-zu](uploads/660bdcd813595f3d6f87d70d6de083d0/DIOT-sb-zu.png)
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![DIOT-sb-zu](uploads/660bdcd813595f3d6f87d70d6de083d0/DIOT-sb-zu.png)
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## Main features and components
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### SoC / FPGA
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| Zynq Ultrascale+ ZU7 | XCZU7CG-1FFVF1517E | 1 | [AFCZ](https://github.com/elhep/AFCZ/wiki) | |
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### Memories
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| PS DDR4 8Gb x5 | MT40A512M16LY-075:E | 5 with ECC | | 8Gb (512M x 16 x 4) |
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| PL DDR4 8Gb | MT40A512M16LY-075:E | 2 | | 8Gb (512M x 16 x 4) |
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| QSPI 512Mbit | MT25QU512ABB | 2 | 7S, ZCU102 | NOR Flash. Xilinx recommends QSPI32 for flash size larger than 16MB (UG1085 v1.9 p233)|
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| eMMC 32Gb | IS21ES04G-JCLI | 1 | 7S | 4Gb x 8 |
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| micro-SD | | 1 | | To simplify board bring-up, later not mounted since eMMC will be used for filesystem. |
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### White Rabbit support
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*See SPEC sch (page 2, 16) and FASEC sch (page 22) for reference*
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| SFP | | 1 | | RD/TD and control signals to FPGA, no need for SFP SYNCE REFCLK like in SPEC |
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| Link/Act LEDs | | 2 | | Placed close to SFP cage (probably SMDs on PCB bottom) |
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| DAC 16-bit | AD5662BRMZ-1 | 2 | SPEC, FASEC, AFCK, (WRS) |
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| Main OSC | VM53S3-25.000-2.5/-30+75 | 1 | SPEC, FASEC, AFCK, WRS | 25 MHz TCXO |
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| Helper VCXO 25MHz | KV7050B25.0000C3GD00 | 1 | eRTM 14 | or compatible with KV7050B25.0000C3GD00 |
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| Helper ext PLL | CDCM61002RHBT | 1 | eRTM14 | Lower jitter than DMTD clock multiplied inside FPGA |
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| (optional) Helper programmable OSC | SI549 | 1 | | Not mounted for CERN |
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| Clock generator | Si5341 | | ZCU102, AFCZ | See [Clocking scheme](https://ohwr.org/project/diot-sb-zu/wikis/home#clocking-scheme). Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
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| | <s>AD9516</s> | | WRS | Not enough clock inputs |
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| Startup OSC | FNETHE025 | 1 | WRS | |
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| I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
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| I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
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| 1-PPS OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal<br> Will be used for WR calibration. |
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| ABSCAL OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal<br> Will be used for WR calibration. |
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### Other oscillators / clock generators
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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### Power
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| Multi-level solution | IRPS5401 | | [Avnet UltraZed](http://zedboard.org/sites/default/files/documentations/AES-ZU3EGES-1-SOM-G-schematics.pdf) | [Infineon PMIC](https://www.infineon.com/cms/en/product/promopages/xilinx-SoC-FPGA-power-reference-design/All-of-Infineons-Zynq-UltraScale-MPSoC-Power-Macros/) |
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| | | | [Maxim power solutions for Xilinx](https://www.maximintegrated.com/en/products/power/switching-regulators/applications/fpga-power/xilinx-fpga-power-solutions/power-solutions-for-xilinx-artix-spartan-and-zynq-fpgas.html/tb_order) |
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### Miscellaneous
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| 12V aux power connector | 4-pin Molex | 1 | -- | For external powering during first tests |
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| Xilinx JTAG connector | MOLEX 87832-1420 | 1 | -- | |
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| Self power-cycle circuit driving backplane PS_ON# | | 1 | | In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail |
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| External watchdog chip for PL | LTC2917HMS-B1#PBF | 1 | FASEC |
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| Thermometers | | 3? | | |
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| 12V header connector for FPGA fan | | 1 | +12V PWM-driven from FPGA, with tachometer pin |
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| FPGA fan control and monitoring | MAX6639AEE+ | | 1 | Provides SMBus interface |
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| Mounting holes for FPGA heatsink | AAVID 342947 | 1 | AFCZ, PXIe FMC carrier | 2 holes for mounting
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| USB UART | CP2108 | 1 | ZCU106 | connected to PS UART and PL pins for dual-USB-UART |
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| Aux clock input | MMCX connector | 1 | | Not mounted on CERN execution of the board. Required by Sinara. |
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### LPC FMC slot with 4 MGTs
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* 68 user-defined I/Os (34 diff-pairs)
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* Voltage translators - Ultrascale has 48 HD I/Os (3.3V max) and 416 HP I/Os (1.8V max)
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* I2C SCL and SDA
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* Present signal
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* 1 LPC MGT
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* 3 HPC MGTs (required for FRAS, EN-SMM)
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* (optional) more HPC MGTs, to be decided later, depending if it will complicate PCB routing
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* FMC clocks connected to dedicated clocking pins of FPGA I/O banks
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* Vadj and I/Os fixed at 1.8V
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### Mechanics
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* Board dimensions: 100mm x 220mm
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* [EDA-03828](https://edms.cern.ch/ui/#!master/navigator/item?P:100130629:100130630:subDocs) to be used as a reference and mechanical template
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* Mechanics of the board shall be compliant with section 3.5.1 of CPCI-S.0 specification.
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* Mechanics of the front panel shall be compliant with sections 3.5.5, 3.5.7 of CPCI-S.0 specification.
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* FMC connector in the front to host a communication mezzanine
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* SFP cage in the front for White Rabbit support
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* CPCIs backplane connectors P1 - P6 in the back
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* ESD strips on both sides of the board, along the bottom edge of the PCB with discharge resistors according to section 3.5.10 of CPCI-S.0 specification.
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* The length of ESD strip segment 2 shall be 115mm.
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### Compact PCI Serial backplane connectors
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* 287 FPGA I/Os in total
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* 8 MGTs (1 MGT per slot) <br>
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* In CERN execution of the board, MGT Tx connected through a capacitor to the backplane connector.<br>
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* As Sinara requires an additional LVDS pair, there will be an option to mount a 0R (L-shaped arrangements of pads with the CAP) instead of the capacitor to connect MGT Tx pair from the backplane to regular PL I/Os.
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* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
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* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
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* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
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* PRST# (P1.H2) - ESD-protected through 3.3V TVS diode
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* PWRBTN# (P1.C3) - ESD-protected through 3.3V TVS diode
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* Monitoring I/Os (PS_ON#, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through 3.3V TVS diode
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* P_PRES0, P_PRES1, M_SDA, M_SCL pulled-up to 3.3V
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* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
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### Clocking scheme
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![clk_scheme](uploads/b67d9037bb68757b7c54232b9bd0c21e/clk_scheme_v2.png)
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### ZU7 HD (3.3V) and HP (1.8V) I/O planning
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| **I/O connector** | **I/O name** | **I/O index** | **No of pins** | **ZU7 I/O bank type** |
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| ------ | ------ | ------ | ------ | ------ |
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| CPCIs backplane | I2C | *P1.B2*, *P1.C2* | 2 | HD |
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| CPCIs backplane | RST# | *P1.F2* | 1 | HD |
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| CPCIs backplane | PWRFAIL# | *P1.F2* | 1 | HD |
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| CPCIs backplane | WAKE_IN# | *P1.I2* | 1 | HD |
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| CPCIs backplane | Monitoring I/Os | *P2 rows 7,8* | 11 | HD |
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| CPCIs backplane | Serial GPIO | *P1.G3*, *P1.H3*, *P1.J3*, *P1.K3* | 4 | HD |
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| CPCIs backplane | PCIe presence detect | *P5.A6*, *P5.C5*, *P5.D6*, *P5.F5*, *P5.G6*, *P5.I5*, *P5.J6*, *P5.L5* | 8 | HD |
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| CPCIs backplane | PWRBTN# | *P1.C3* | 1 | HD |
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| CPCIs backplane | PRST# | *P1.H2* | 1 | HD |
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| CPCIs backplane | PCIe/USB/SATA/Eth | * | 288 | HP |
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| FMC connector | User-defined signals | *LA[00..33]_P/N* | 68 | HP |
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## Related links and documents
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## Related links and documents
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* [Board specification](https://ohwr.org/project/diot-sb-zu/wikis/Board-specification)
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## Contacts
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## Contacts
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* [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch) - CERN
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* [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch) - CERN
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