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# DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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See https://ohwr.org/project/diot/wikis/diot-fmc-carrier
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This page gathers the design specification of the FMC carrier Peripheral Board for DI/OT crate. The role of this board is to provide the ability to host FMC mezzanines inside the DI/OT crate. It is equipped with an FPGA that communicates over the DI/OT backplane with a DI/OT System Board using a Multi Gigabit Transceiver (MGT) and provides I/Os to the FMC connector.
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## Specification
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Wherever possible, the same components shall be used as in the [DI/OT ZU7 System Board](https://ohwr.org/project/diot-sb-zu/tree/master/hw)
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### Components
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#### FPGA
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* **Kintex Ultrascale** - XCKU035-1FFVA1156C
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* Example I/O assignment to various HP/HR I/O banks
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|**Bank**|**Voltage**|**Assignment**|
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|----|----|----|
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| 64 (HR) | * | P4 signals, peripherals |
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| 65 (HR) | * | DI/OT backplane P1 slow I/Os, peripherals, thermometers, LEDs |
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| 66 (HP) | 1.2V | DDR4 |
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| 67 (HP) | 1.2V | DDR4 |
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| 68 (HP) | 1.2V | DDR4 |
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| 44 (HP) | 1.8V | DI/OT backplane P1/P6 LVDS lanes, CLK |
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| 45 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
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| 46 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
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| 47 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
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| 48 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
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#### FMC
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* **HPC** with 8 MGTs - to e.g. host COTS ADC FMCs, DACs with JESD204B
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* **Vadj** 1.8V enabled/disabled by FPGA pin
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#### DI/OT backplane connectors
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* **P1** fully populated:
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* *MGT_Tx/MGT_Rx* lanes connected to FPGA transceiver
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* LVDS lanes (*DIFF0..10*) connected to FPGA I/Os, from those *DIFF0* and *DIFF8* connected to clock-capable FPGA I/Os
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* Geographical addressing pins (*GA0..3*) connected to FPGA I/Os
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* *SHARED_BUS0..4* connected to FPGA I/Os
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* *RST_N* connected to FPGA I/O
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* *SYSEN_N* connected to FPGA I/O
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* *CLK_P/CLK_N* connected to Si5341
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* **P6**:
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* LVDS lanes (*DIFF11..14*) connected to FPGA I/Os
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* **P4** populated depending on FPGA I/Os availability:
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* *RTM_SHARED_BUS0..7* connected to FPGA I/Os through switches (e.g. 74HC4066PW) all enabled from 1 FPGA pin - to allow peripheral board to be dynamically attached to the P4 shared bus.
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* RTM I/Os connected to FPGA I/Os depending on available I/Os
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#### Connectivity
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* front-panel, ideally includes
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- LEDs connected to FPGA I/Os (4-6? depending how many can be fit in the front panel)
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- a DIO with lemo-00
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#### Memories
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* **DDR4 SO-DIMM** slot - not all applications will need external memory + it will make memory obsolescence handling easier
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* **QSPI Flash** - for FPGA bitstream
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* **24AA025E48-I/SN** EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board (see [details on Peripheral Boards identification](https://ohwr.org/project/diot/wikis/crate_monitoring) )
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* [optional] eMMC / microSD card slot - if spare FPGA pins are available
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#### Clock generation
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* Si5341 for main FPGA clock, DDR clock, MGT clocks
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* operating in zero delay mode (external feedback loop from *out9* to *fb_in*)
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* local oscillator or CLK_P/N from DI/OT backplane as possible clock inputs
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* optional DRTIO oscillators
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#### Power
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* IRPS5401 PMIC
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* separate DC/DC for Vadj generation; its *enable* input shall be controlled by FPGA. The same Vadj shall power FPGA I/O banks that are connected to FMC I/Os so that Vadj can be turned on ONLY when FMC mezzanine supported voltages match carrier supported voltage (1.8V).
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#### Miscellaneous
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* Xilinx JTAG connector: **MOLEX 87832-1420**
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* Thermometers
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* LEDs in the front panel
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* FPGA heatsink (same as on [DI/OT ZU7 System Board](https://ohwr.org/project/diot-sb-zu/tree/master/hw))
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* External power connector to run the board without DI/OT crate (4-pin Molex same as on [DI/OT ZU7 System Board](https://ohwr.org/project/diot-sb-zu/tree/master/hw))
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#### Mechanical
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* 100mm x 220mm
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* **P1**, **P4** and **P6** backplane connectors
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* cut-out in PCB under the FMC slot (like in SPEC board, for better cooling).
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* [DIO 16ch opt 24V](https://edms.cern.ch/ui/#!master/navigator/item?P:100130669:100130670:subDocs) as mechanical reference
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### Requirements
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* The board shall have EEPROM-based identification mechanism implemented according to [Peripheral Boards identification procedure](https://ohwr.org/project/diot/wikis/crate_monitoring#peripheral-boards-identification)
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* the same SERVMOD_N signal shall drive:
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- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
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- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
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* Backplane P1 connector pins shall have dual IO/JTAG function (selectable with SERVMOD_N):
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- *A3* - TDI
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- *D3* - TDO
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- *B4* - TMS
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- *H4* - TCK
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- *K4* - nTRST
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* MGT backplane lanes (P1.A5,A6,D5,E5) shall be connected to FPGA MGT
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### To be defined:
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* Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
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- A TE/ABT: JTAG to backplane please
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## Contacts
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* [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch) - CERN
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## Status
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| Date | Event |
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| --------- | ------ |
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| May-2020 | Project starts, gathering specification | |