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# Cute-WR-A7 (Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7)
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# Cute-WR-A7
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# (Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7)
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## Introduction
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The cute-wr series are standalone White Rabbit Node implementation on FPGA Mezzanine Card. The idea is to have a compact, low-cost and common WR NIC for synchronous DAQ frontends and other applications!
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[Cute-WR](https://www.ohwr.org/project/cute-wr/wiki) shows the feasibility fo this idea; while the [Cute-WR-DP](https://www.ohwr.org/project/cute-wr-dp/wiki) expands the Cute-WR to two SFP ports that can support various operation modes.
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The Cute-WR series are standalone White Rabbit Node implementations on FPGA Mezzanine Card form factor. The idea is to have a compact, low-cost and common WR NIC for synchronous DAQ front-ends and other applications!
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[Cute-WR](https://www.ohwr.org/project/cute-wr/wiki) shows the feasibility of the idea; while the [Cute-WR-DP](https://www.ohwr.org/project/cute-wr-dp/wiki) expands the Cute-WR to two SFP ports that can support various operation modes.
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The Cute-WR-A7 is the enhanced version of the CUTE-WR-DP with an Xilinx Artix7 series FPGA. It inherits similar interfaces from Cute-WR-DP: two SFP ports, two SMA/LEMO connectors, FMC form factor with LPC connector, etc.
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The three operation modes of Cute-WR-DP are also supported by Cute-WR-A7:
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