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*Everything below is sample text - to be
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replaced\>**
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[![](/project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)](/project/white-rabbit/uploads/0eeb5b430351eca8a4e76a5af3892c2c/svectop_l.png)
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[![](https://www.ohwr.org//project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)](https://www.ohwr.org//project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)
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*SVEC V1 production board**
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## Main Features
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MHz (Silicon Labs Si570, freely usable)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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core](https://www.ohwr.org/project/wr-cores/wikis))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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core](https://www.ohwr.org/project/wr-cores/wikis))
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- 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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core](https://www.ohwr.org/project/wr-cores/wikis))
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- On-board memories
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- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16HA-15E)
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- 1x 128 Mbit SPI flash for FPGA firmware storage
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## Project information
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- Official production documentation:
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[EDA-0](http://edms.cern.ch/nav/eda-0)
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none
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- [Users](Users)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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