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Conv TTL RS485 - Testing
Commit e35f6bbc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl: Added logic for the SFP tests 

The EEPROM test doesn't work yet, but that may be related to the wrong-ish SFP
connector placed on the board.

Lengthy clarification: the PTS for the CONV-TTL-RS485 boards is inspired from
the PTS of CONV-TTL-BLO, where an SFP+ connector is used. Since the
CONV-TTL-RS485 uses just an SFP connector (not the SFP+), there might be
something wrong when reading the I2C interface. Reading the manuals yielded no
relevant reasons why this would occur, but I'm still investigating.

Either way, the link up test works, just the EEPROM test needs to be clarified
why it doesn't work. And the SFP changed for an SFP+.
parent aaeaed1f
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Showing with 319 additions and 3 deletions
hdl/top/pts.ucf
View file @ e35f6bbc
......@@ -307,6 +307,18 @@ NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = D2;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# FPGA MGT lines
#-----------------------------------------------------------------------------
NET "mgt_clk0_p_i" LOC = A10;
NET "mgt_clk0_n_i" LOC = B10;
NET "mgt_sfp_rx0_p_i" LOC = D7;
NET "mgt_sfp_rx0_n_i" LOC = C7;
NET "mgt_sfp_tx0_p_o" LOC = B6;
NET "mgt_sfp_tx0_n_o" LOC = A6;
#=============================================================================
# OTHER SIGNALS
#=============================================================================
......
hdl/top/pts.vhd
View file @ e35f6bbc
......@@ -46,6 +46,9 @@ use work.conv_common_gw_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrcore_pkg.all;
use work.endpoint_pkg.all;
entity pts is
port
......@@ -114,6 +117,14 @@ entity pts is
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- FPGA MGT lines
mgt_clk0_p_i : in std_logic;
mgt_clk0_n_i : in std_logic;
mgt_sfp_rx0_p_i : in std_logic;
mgt_sfp_rx0_n_i : in std_logic;
mgt_sfp_tx0_p_o : out std_logic;
mgt_sfp_tx0_n_o : out std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
......@@ -500,6 +511,49 @@ architecture arch of pts is
);
end component clk_info_wb_slave;
-- GTP component
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_force_disparity : integer;
g_enable_ch0 : integer;
g_enable_ch1 : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch1_ref_clk_i : in std_logic := '0';
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
--============================================================================
-- Signal declarations
--============================================================================
......@@ -574,6 +628,42 @@ architecture arch of pts is
signal cnt_20_actual_rst : std_logic;
signal dac_20_sync_n : std_logic_vector(7 downto 0);
-- SFP EEPROM signals
signal i2c_scl_fr_sfp : std_logic;
signal i2c_scl_to_sfp : std_logic;
signal i2c_sfp_scl_en : std_logic;
signal i2c_sda_fr_sfp : std_logic;
signal i2c_sda_to_sfp : std_logic;
signal i2c_sfp_sda_en : std_logic;
-- SFP signals
signal clk_gtp : std_logic;
signal minic_mem_data_out : std_logic_vector(31 downto 0);
signal minic_mem_addr_out : std_logic_vector(c_minic_memsize_log2-1 downto 0);
signal minic_mem_data_in : std_logic_vector(31 downto 0);
signal minic_mem_wr : std_logic;
signal minic_src_out : t_wrf_source_out;
signal minic_src_in : t_wrf_source_in;
signal minic_snk_out : t_wrf_sink_out;
signal minic_snk_in : t_wrf_sink_in;
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_tx_d : std_logic_vector(15 downto 0);
signal phy_tx_k : std_logic_vector( 1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_error : std_logic;
signal phy_rx_d : std_logic_vector(15 downto 0);
signal phy_rx_clk : std_logic;
signal phy_rx_k : std_logic_vector( 1 downto 0);
signal phy_rx_error : std_logic;
signal phy_rx_bitslide : std_logic_vector( 4 downto 0);
signal dpram_we : std_logic;
signal dpram_ack : std_logic;
-- one-wire master signals
signal owr_pwren : std_logic_vector(0 downto 0);
signal owr_en : std_logic_vector(0 downto 0);
......@@ -1053,6 +1143,222 @@ begin
-- Finally, assign the SYNC_N output to the DAC
dac_125_sync_n_o <= dac_125_sync_n(0);
--============================================================================
-- SFP EEPROM test logic
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an I2C master to handle SFP communication
cmp_sfp_eeprom_i2c : wb_i2c_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_adr_i => xbar_master_out(c_slv_sfp_i2c).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_sfp_i2c).dat,
wb_we_i => xbar_master_out(c_slv_sfp_i2c).we,
wb_stb_i => xbar_master_out(c_slv_sfp_i2c).stb,
wb_sel_i => xbar_master_out(c_slv_sfp_i2c).sel,
wb_cyc_i => xbar_master_out(c_slv_sfp_i2c).cyc,
wb_ack_o => xbar_master_in(c_slv_sfp_i2c).ack,
wb_int_o => xbar_master_in(c_slv_sfp_i2c).int,
wb_dat_o => xbar_master_in(c_slv_sfp_i2c).dat,
scl_pad_i => i2c_scl_fr_sfp,
scl_pad_o => i2c_scl_to_sfp,
scl_padoen_o => i2c_sfp_scl_en,
sda_pad_i => i2c_sda_fr_sfp,
sda_pad_o => i2c_sda_to_sfp,
sda_padoen_o => i2c_sfp_sda_en
);
-- and assign the ports and tri-state buffers
sfp_mod_def1_b <= i2c_scl_to_sfp when (i2c_sfp_scl_en = '0') else 'Z';
i2c_scl_fr_sfp <= sfp_mod_def1_b;
sfp_mod_def2_b <= i2c_sda_to_sfp when (i2c_sfp_sda_en = '0') else 'Z';
i2c_sda_fr_sfp <= sfp_mod_def2_b;
--============================================================================
-- SFP loopback test logic
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an IBUFGDS for MGT clock
cmp_mgt_clk_ibufds : IBUFDS
generic map
(
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT"
)
port map
(
I => mgt_clk0_p_i,
IB => mgt_clk0_n_i,
O => clk_gtp
);
-- Connect the MINIC module to the crossbar
cmp_sfp_minic : xwr_mini_nic
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_memsize_log2 => c_minic_memsize_log2,
g_buffer_little_endian => true
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
mem_data_o => minic_mem_data_out,
mem_addr_o => minic_mem_addr_out,
mem_data_i => minic_mem_data_in,
mem_wr_o => minic_mem_wr,
src_o => minic_src_out,
src_i => minic_src_in,
snk_o => minic_snk_out,
snk_i => minic_snk_in,
txtsu_port_id_i => "00000",
txtsu_frame_id_i => x"0000",
txtsu_tsval_i => x"00000000",
txtsu_tsincorrect_i => '0',
txtsu_stb_i => '0',
wb_i => xbar_master_out(c_slv_minic),
wb_o => xbar_master_in(c_slv_minic)
);
-- Connect the endpoint buffer RAM
cmp_sfp_dpram : generic_dpram
generic map
(
g_data_width => 32,
g_size => 2**c_minic_memsize_log2,
g_with_byte_enable => false,
g_dual_clock => false
)
port map
(
rst_n_i => rst_20_n,
clka_i => clk_20_i,
bwea_i => "0000",
wea_i => dpram_we,
aa_i => xbar_master_out(c_slv_dpram).adr(c_minic_memsize_log2+1 downto 2),
da_i => xbar_master_out(c_slv_dpram).dat,
qa_o => xbar_master_in(c_slv_dpram).dat,
clkb_i => clk_20_i,
bweb_i => "0000",
web_i => minic_mem_wr,
ab_i => minic_mem_addr_out,
db_i => minic_mem_data_out,
qb_o => minic_mem_data_in
);
-- associate WE to first port of the RAM to WB signals
dpram_we <= xbar_master_out(c_slv_dpram).cyc and xbar_master_out(c_slv_dpram).stb and
xbar_master_out(c_slv_dpram).we;
-- ACK logic for DPRAM
xbar_master_in(c_slv_dpram).ack <= dpram_ack;
xbar_master_in(c_slv_dpram).err <= '0';
p_ram_ack : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
dpram_ack <= '0';
else
dpram_ack <= '0';
if (xbar_master_out(c_slv_dpram).stb = '1') and
(xbar_master_out(c_slv_dpram).cyc = '1') then
dpram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
-- Connect the Endpoint module to the crossbar
cmp_sfp_endpoint : xwr_endpoint
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_simulation => false,
g_tx_force_gap_length => 0,
g_pcs_16bit => false,
g_rx_buffer_size => 1024,
g_with_rx_buffer => true,
g_with_flow_control => false,
g_with_timestamper => true,
g_with_dpi_classifier => false,
g_with_vlans => false,
g_with_rtu => false,
g_with_leds => false,
g_with_dmtd => false
)
port map
(
clk_ref_i => clk_125,
clk_sys_i => clk_20_i,
clk_dmtd_i => clk_125,
rst_n_i => rst_20_n,
pps_csync_p1_i => '0',
pps_valid_i => '0',
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_ref_clk_i => clk_125,
phy_tx_data_o => phy_tx_d,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_error,
phy_rx_data_i => phy_rx_d,
phy_rx_clk_i => phy_rx_clk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_error,
phy_rx_bitslide_i => phy_rx_bitslide,
src_o => minic_snk_in,
src_i => minic_snk_out,
snk_o => minic_src_in,
snk_i => minic_src_out,
wb_i => xbar_master_out(c_slv_endpoint),
wb_o => xbar_master_in(c_slv_endpoint)
);
-- Finally, connect the GTP transceiver to the endpoint signals
cmp_gtp_xceiver : wr_gtp_phy_spartan6
generic map
(
g_simulation => 0,
g_force_disparity => 1,
g_enable_ch0 => 1,
g_enable_ch1 => 0
)
port map
(
gtp_clk_i => clk_gtp,
ch0_ref_clk_i => clk_125,
ch0_tx_data_i => phy_tx_d(7 downto 0),
ch0_tx_k_i => phy_tx_k(0),
ch0_tx_disparity_o => phy_tx_disparity,
ch0_tx_enc_err_o => phy_tx_error,
ch0_rx_rbclk_o => phy_rx_clk,
ch0_rx_data_o => phy_rx_d(7 downto 0),
ch0_rx_k_o => phy_rx_k(0),
ch0_rx_enc_err_o => phy_rx_error,
ch0_rx_bitslide_o => phy_rx_bitslide(3 downto 0),
ch0_rst_i => phy_rst,
ch0_loopen_i => phy_loopen,
pad_txn0_o => mgt_sfp_tx0_n_o,
pad_txp0_o => mgt_sfp_tx0_p_o,
pad_rxn0_i => mgt_sfp_rx0_n_i,
pad_rxp0_i => mgt_sfp_rx0_p_i
);
--============================================================================
-- Thermometer test logic
--============================================================================
......@@ -1497,12 +1803,10 @@ begin
flash_mosi_o <= '0';
flash_sclk_o <= '0';
rs485_oen_o <= '0';
rs485_oen_o <= '0';
-- SFP lines all open-drain, set to high-impedance
sfp_rate_select_o <= 'Z';
sfp_mod_def1_b <= 'Z';
sfp_mod_def2_b <= 'Z';
sfp_tx_disable_o <= 'Z';
end architecture arch;
......
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