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Conv TTL RS485 - Testing
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Conv TTL RS485 - Testing
Commits
8c67bd8c
Commit
8c67bd8c
authored
Sep 28, 2018
by
Denia Bouhired-Ferrag
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PTS HDL: added project file and wbgen generated files for doc
parent
83d9c4f9
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4 changed files
with
20 additions
and
368 deletions
+20
-368
pts_regs.htm
hdl/modules/pts_regs.htm
+14
-323
pts_regs.tex
hdl/modules/pts_regs.tex
+1
-40
pulse_cnt_wb.vhd
hdl/modules/pulse_cnt_wb.vhd
+4
-4
pts.xise
hdl/syn/pts.xise
+1
-1
No files found.
hdl/modules/pts_regs.htm
l
→
hdl/modules/pts_regs.htm
View file @
8c67bd8c
...
...
@@ -38,7 +38,6 @@
<span
style=
"margin-left: 20px; "
>
3.2.
<A
href=
"#sect_3_2"
>
CSR
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.3.
<A
href=
"#sect_3_3"
>
LSR
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.4.
<A
href=
"#sect_3_4"
>
TER
</a></span><br/>
<span
style=
"margin-left: 20px; "
>
3.5.
<A
href=
"#sect_3_5"
>
HWVERS
</a></span><br/>
<h3><a
name=
"sect_1_0"
>
1. Memory map summary
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
...
...
@@ -126,23 +125,6 @@ pts_ter
TER
</td>
</tr>
<tr
class=
"tr_odd"
>
<td
class=
"td_code"
>
0x4
</td>
<td
>
REG
</td>
<td
>
<A
href=
"#HWVR"
>
HWVERS
</a>
</td>
<td
class=
"td_code"
>
pts_hwvr
</td>
<td
class=
"td_code"
>
HWVR
</td>
</tr>
</table>
<h3><a
name=
"sect_2_0"
>
2. HDL symbol
</a></h3>
...
...
@@ -186,7 +168,7 @@ pts_bidr_i[31:0]
⇒
</td>
<td
class=
"td_pblock_left"
>
wb_adr_i[
2
:0]
wb_adr_i[
1
:0]
</td>
<td
class=
"td_sym_center"
>
...
...
@@ -816,46 +798,12 @@ pts_ter_oterm_o[5:0]
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
<b>
HWVERS:
</b>
</td>
<td
class=
"td_arrow_right"
>
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
pts_hwvr_hwvers_i[5:0]
pts_ter_hwvers_i[5:0]
</td>
<td
class=
"td_arrow_right"
>
⇐
...
...
@@ -1849,23 +1797,23 @@ Termination Enable Register
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unuse
d"
>
-
<td
style=
"border: solid 1px black;"
colspan=
6
class=
"td_fiel
d"
>
HWVERS[5:0]
</td>
<td
class=
"td_unused"
>
-
<td
>
</td>
<td
class=
"td_unused"
>
-
<td
>
</td>
<td
class=
"td_unused"
>
-
<td
>
</td>
<td
class=
"td_unused"
>
-
<td
>
</td>
<td
class=
"td_unused"
>
-
<td
>
</td>
</tr>
</table>
...
...
@@ -1986,263 +1934,6 @@ ITERM
OTERM
</b>
[
<i>
read/write
</i>
]: Output termination enable
<br>
Set high to enable the channel output terminations
<br>
Bit 0 -- channel 1
<br>
Bit 1 -- channel 2
<br>
etc.
</ul>
<a
name=
"HWVR"
></a>
<h3><a
name=
"sect_3_5"
>
3.5. HWVERS
</a></h3>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
>
<b>
HW prefix:
</b>
</td>
<td
class=
"td_code"
>
pts_hwvr
</td>
</tr>
<tr>
<td
>
<b>
HW address:
</b>
</td>
<td
class=
"td_code"
>
0x4
</td>
</tr>
<tr>
<td
>
<b>
C prefix:
</b>
</td>
<td
class=
"td_code"
>
HWVR
</td>
</tr>
<tr>
<td
>
<b>
C offset:
</b>
</td>
<td
class=
"td_code"
>
0x10
</td>
</tr>
</table>
<p>
Hardware version register
</p>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
31
</td>
<td
class=
"td_bit"
>
30
</td>
<td
class=
"td_bit"
>
29
</td>
<td
class=
"td_bit"
>
28
</td>
<td
class=
"td_bit"
>
27
</td>
<td
class=
"td_bit"
>
26
</td>
<td
class=
"td_bit"
>
25
</td>
<td
class=
"td_bit"
>
24
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
23
</td>
<td
class=
"td_bit"
>
22
</td>
<td
class=
"td_bit"
>
21
</td>
<td
class=
"td_bit"
>
20
</td>
<td
class=
"td_bit"
>
19
</td>
<td
class=
"td_bit"
>
18
</td>
<td
class=
"td_bit"
>
17
</td>
<td
class=
"td_bit"
>
16
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
15
</td>
<td
class=
"td_bit"
>
14
</td>
<td
class=
"td_bit"
>
13
</td>
<td
class=
"td_bit"
>
12
</td>
<td
class=
"td_bit"
>
11
</td>
<td
class=
"td_bit"
>
10
</td>
<td
class=
"td_bit"
>
9
</td>
<td
class=
"td_bit"
>
8
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
</tr>
</table>
<table
cellpadding=
0
cellspacing=
0
border=
0
>
<tr>
<td
class=
"td_bit"
>
7
</td>
<td
class=
"td_bit"
>
6
</td>
<td
class=
"td_bit"
>
5
</td>
<td
class=
"td_bit"
>
4
</td>
<td
class=
"td_bit"
>
3
</td>
<td
class=
"td_bit"
>
2
</td>
<td
class=
"td_bit"
>
1
</td>
<td
class=
"td_bit"
>
0
</td>
</tr>
<tr>
<td
class=
"td_unused"
>
-
</td>
<td
class=
"td_unused"
>
-
</td>
<td
style=
"border: solid 1px black;"
colspan=
6
class=
"td_field"
>
HWVERS[5:0]
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
<td
>
</td>
</tr>
</table>
<ul>
<li><b>
HWVERS
</b>
[
<i>
read-only
</i>
]: PCB version number
...
...
hdl/modules/pts_regs.tex
View file @
8c67bd8c
...
...
@@ -12,7 +12,6 @@
0x4
&
REG
&
CSR
&
pts
\_
csr
&
CSR
\\
0x8
&
REG
&
LSR
&
pts
\_
lsr
&
LSR
\\
0xc
&
REG
&
TER
&
pts
\_
ter
&
TER
\\
0x10
&
REG
&
HWVERS
&
pts
\_
hwvr
&
HWVR
\\
\hline
\end{tabular}
}
...
...
@@ -307,7 +306,7 @@ Termination Enable Register
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
-
&
-
&
-
&
-
&
-
&
\multicolumn
{
1
}{
c|
}{
-
}
\\
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
\multicolumn
{
6
}{
|c|
}{
\cellcolor
{
RoyalPurple!25
}
HWVERS[5:0]
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
...
...
@@ -335,44 +334,6 @@ OTERM
\\
Set high to enable the channel output terminations
\\
Bit 0 -- channel 1
\\
Bit 1 -- channel 2
\\
etc.
\end{small}
\end{itemize}
\paragraph*
{
HWVERS
}
\vspace
{
12pt
}
\rowcolors
{
1
}{
white
}{
white
}
\begin{tabular}
{
l l
}
{
\bf
HW prefix:
}
&
pts
\_
hwvr
\\
{
\bf
HW address:
}
&
0x4
\\
{
\bf
SW prefix:
}
&
HWVR
\\
{
\bf
SW offset:
}
&
0x10
\\
\end{tabular}
\vspace
{
12pt
}
Hardware version register
\vspace
{
12pt
}
\noindent
\resizebox
{
\textwidth
}{
!
}{
\begin{tabular}
{
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
>
{
\centering\arraybackslash
}
p
{
1.5cm
}
}
31
&
30
&
29
&
28
&
27
&
26
&
25
&
24
\\
\hline
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
-
&
-
&
-
&
-
&
-
&
\multicolumn
{
1
}{
c|
}{
-
}
\\
\hline
23
&
22
&
21
&
20
&
19
&
18
&
17
&
16
\\
\hline
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
-
&
-
&
-
&
-
&
-
&
\multicolumn
{
1
}{
c|
}{
-
}
\\
\hline
15
&
14
&
13
&
12
&
11
&
10
&
9
&
8
\\
\hline
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
-
&
-
&
-
&
-
&
-
&
\multicolumn
{
1
}{
c|
}{
-
}
\\
\hline
7
&
6
&
5
&
4
&
3
&
2
&
1
&
0
\\
\hline
\multicolumn
{
1
}{
|c
}{
-
}
&
-
&
\multicolumn
{
6
}{
|c|
}{
\cellcolor
{
RoyalPurple!25
}
HWVERS[5:0]
}
\\
\hline
\end{tabular}
}
\begin{itemize}
\item
\begin{small}
{
\bf
HWVERS
...
...
hdl/modules/pulse_cnt_wb.vhd
View file @
8c67bd8c
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created :
Mon Nov 3 09:56:02 2014
-- File :
.\
pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from
.\
pulse_cnt_wb.wb
-- Created :
01/26/18 11:52:56
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
.\
pulse_cnt_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
hdl/syn/pts.xise
View file @
8c67bd8c
...
...
@@ -49,7 +49,7 @@
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"false"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
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