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Conv TTL RS485 - Testing
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Conv TTL RS485 - Testing
Commits
5af5ba24
Commit
5af5ba24
authored
Oct 31, 2014
by
Theodor-Adrian Stana
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hdl: Implemented logic for TTL pulse test
parent
8a61389f
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6 changed files
with
1338 additions
and
492 deletions
+1338
-492
Manifest.py
hdl/modules/Manifest.py
+2
-1
pulse_cnt_wb.vhd
hdl/modules/pulse_cnt_wb.vhd
+353
-129
pulse_cnt_wb.wb
hdl/modules/pulse_cnt_wb.wb
+243
-210
pulse_gen_gp.vhd
hdl/modules/pulse_gen_gp.vhd
+165
-0
pts.xise
hdl/syn/pts.xise
+125
-122
pts.vhd
hdl/top/pts.vhd
+450
-30
No files found.
hdl/modules/Manifest.py
View file @
5af5ba24
...
...
@@ -2,5 +2,6 @@ files = [
"pts_regs.vhd"
,
"pulse_cnt_wb.vhd"
,
"incr_counter.vhd"
,
"clk_info_wb_slave.vhd"
"clk_info_wb_slave.vhd"
,
"pulse_gen_gp.vhd"
]
hdl/modules/pulse_cnt_wb.vhd
View file @
5af5ba24
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created :
Tue Apr 30 08:48:19 2013
-- Created :
Fri Oct 31 14:58:53 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
...
...
@@ -27,70 +27,134 @@ entity pulse_cnt_wb is
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH7 output'
pulse_cnt_ch7o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH7 input'
pulse_cnt_ch7i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH8 output'
pulse_cnt_ch8o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH8 input'
pulse_cnt_ch8i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH9 output'
pulse_cnt_ch9o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH9 input'
pulse_cnt_ch9i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 output'
pulse_cnt_ch10o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 input'
pulse_cnt_ch10i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH11 output'
pulse_cnt_ch11o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH11 input'
pulse_cnt_ch11i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH12 output'
pulse_cnt_ch12o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH12 input'
pulse_cnt_ch12i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH13 output'
pulse_cnt_ch13o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH13 input'
pulse_cnt_ch13i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH14 output'
pulse_cnt_ch14o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH14 input'
pulse_cnt_ch14i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH15 output'
pulse_cnt_ch15o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH15 input'
pulse_cnt_ch15i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH16 output'
pulse_cnt_ch16o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH16 input'
pulse_cnt_ch16i_val_i
:
in
std_logic_vector
(
31
downto
0
)
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1OCR'
pulse_cnt_ttlch1o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1ICR'
pulse_cnt_ttlch1i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2OCR'
pulse_cnt_ttlch2o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2ICR'
pulse_cnt_ttlch2i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3OCR'
pulse_cnt_ttlch3o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3ICR'
pulse_cnt_ttlch3i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4OCR'
pulse_cnt_ttlch4o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4ICR'
pulse_cnt_ttlch4i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5OCR'
pulse_cnt_ttlch5o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5ICR'
pulse_cnt_ttlch5i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6OCR'
pulse_cnt_ttlch6o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6ICR'
pulse_cnt_ttlch6i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAOCR'
pulse_cnt_invttlchao_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchao_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchao_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAICR'
pulse_cnt_invttlchai_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchai_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchai_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBOCR'
pulse_cnt_invttlchbo_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbo_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbo_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBICR'
pulse_cnt_invttlchbi_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbi_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbi_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCOCR'
pulse_cnt_invttlchco_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchco_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchco_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCICR'
pulse_cnt_invttlchci_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchci_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchci_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDOCR'
pulse_cnt_invttlchdo_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdo_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdo_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDICR'
pulse_cnt_invttlchdi_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdi_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdi_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1OCR'
pulse_cnt_rearch1o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1ICR'
pulse_cnt_rearch1i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2OCR'
pulse_cnt_rearch2o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2ICR'
pulse_cnt_rearch2i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3OCR'
pulse_cnt_rearch3o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3ICR'
pulse_cnt_rearch3i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4OCR'
pulse_cnt_rearch4o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4ICR'
pulse_cnt_rearch4i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5OCR'
pulse_cnt_rearch5o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5ICR'
pulse_cnt_rearch5i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6OCR'
pulse_cnt_rearch6o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch6o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch6o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
pulse_cnt_rearch16_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch16_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch16_load_o
:
out
std_logic
);
end
pulse_cnt_wb
;
...
...
@@ -123,208 +187,336 @@ begin
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
pulse_cnt_ttlch1o_load_o
<=
'0'
;
pulse_cnt_ttlch1i_load_o
<=
'0'
;
pulse_cnt_ttlch2o_load_o
<=
'0'
;
pulse_cnt_ttlch2i_load_o
<=
'0'
;
pulse_cnt_ttlch3o_load_o
<=
'0'
;
pulse_cnt_ttlch3i_load_o
<=
'0'
;
pulse_cnt_ttlch4o_load_o
<=
'0'
;
pulse_cnt_ttlch4i_load_o
<=
'0'
;
pulse_cnt_ttlch5o_load_o
<=
'0'
;
pulse_cnt_ttlch5i_load_o
<=
'0'
;
pulse_cnt_ttlch6o_load_o
<=
'0'
;
pulse_cnt_ttlch6i_load_o
<=
'0'
;
pulse_cnt_invttlchao_load_o
<=
'0'
;
pulse_cnt_invttlchai_load_o
<=
'0'
;
pulse_cnt_invttlchbo_load_o
<=
'0'
;
pulse_cnt_invttlchbi_load_o
<=
'0'
;
pulse_cnt_invttlchco_load_o
<=
'0'
;
pulse_cnt_invttlchci_load_o
<=
'0'
;
pulse_cnt_invttlchdo_load_o
<=
'0'
;
pulse_cnt_invttlchdi_load_o
<=
'0'
;
pulse_cnt_rearch1o_load_o
<=
'0'
;
pulse_cnt_rearch1i_load_o
<=
'0'
;
pulse_cnt_rearch2o_load_o
<=
'0'
;
pulse_cnt_rearch2i_load_o
<=
'0'
;
pulse_cnt_rearch3o_load_o
<=
'0'
;
pulse_cnt_rearch3i_load_o
<=
'0'
;
pulse_cnt_rearch4o_load_o
<=
'0'
;
pulse_cnt_rearch4i_load_o
<=
'0'
;
pulse_cnt_rearch5o_load_o
<=
'0'
;
pulse_cnt_rearch5i_load_o
<=
'0'
;
pulse_cnt_rearch6o_load_o
<=
'0'
;
pulse_cnt_rearch16_load_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
pulse_cnt_ttlch1o_load_o
<=
'0'
;
pulse_cnt_ttlch1i_load_o
<=
'0'
;
pulse_cnt_ttlch2o_load_o
<=
'0'
;
pulse_cnt_ttlch2i_load_o
<=
'0'
;
pulse_cnt_ttlch3o_load_o
<=
'0'
;
pulse_cnt_ttlch3i_load_o
<=
'0'
;
pulse_cnt_ttlch4o_load_o
<=
'0'
;
pulse_cnt_ttlch4i_load_o
<=
'0'
;
pulse_cnt_ttlch5o_load_o
<=
'0'
;
pulse_cnt_ttlch5i_load_o
<=
'0'
;
pulse_cnt_ttlch6o_load_o
<=
'0'
;
pulse_cnt_ttlch6i_load_o
<=
'0'
;
pulse_cnt_invttlchao_load_o
<=
'0'
;
pulse_cnt_invttlchai_load_o
<=
'0'
;
pulse_cnt_invttlchbo_load_o
<=
'0'
;
pulse_cnt_invttlchbi_load_o
<=
'0'
;
pulse_cnt_invttlchco_load_o
<=
'0'
;
pulse_cnt_invttlchci_load_o
<=
'0'
;
pulse_cnt_invttlchdo_load_o
<=
'0'
;
pulse_cnt_invttlchdi_load_o
<=
'0'
;
pulse_cnt_rearch1o_load_o
<=
'0'
;
pulse_cnt_rearch1i_load_o
<=
'0'
;
pulse_cnt_rearch2o_load_o
<=
'0'
;
pulse_cnt_rearch2i_load_o
<=
'0'
;
pulse_cnt_rearch3o_load_o
<=
'0'
;
pulse_cnt_rearch3i_load_o
<=
'0'
;
pulse_cnt_rearch4o_load_o
<=
'0'
;
pulse_cnt_rearch4i_load_o
<=
'0'
;
pulse_cnt_rearch5o_load_o
<=
'0'
;
pulse_cnt_rearch5i_load_o
<=
'0'
;
pulse_cnt_rearch6o_load_o
<=
'0'
;
pulse_cnt_rearch16_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
pulse_cnt_ttlch1o_load_o
<=
'0'
;
pulse_cnt_ttlch1i_load_o
<=
'0'
;
pulse_cnt_ttlch2o_load_o
<=
'0'
;
pulse_cnt_ttlch2i_load_o
<=
'0'
;
pulse_cnt_ttlch3o_load_o
<=
'0'
;
pulse_cnt_ttlch3i_load_o
<=
'0'
;
pulse_cnt_ttlch4o_load_o
<=
'0'
;
pulse_cnt_ttlch4i_load_o
<=
'0'
;
pulse_cnt_ttlch5o_load_o
<=
'0'
;
pulse_cnt_ttlch5i_load_o
<=
'0'
;
pulse_cnt_ttlch6o_load_o
<=
'0'
;
pulse_cnt_ttlch6i_load_o
<=
'0'
;
pulse_cnt_invttlchao_load_o
<=
'0'
;
pulse_cnt_invttlchai_load_o
<=
'0'
;
pulse_cnt_invttlchbo_load_o
<=
'0'
;
pulse_cnt_invttlchbi_load_o
<=
'0'
;
pulse_cnt_invttlchco_load_o
<=
'0'
;
pulse_cnt_invttlchci_load_o
<=
'0'
;
pulse_cnt_invttlchdo_load_o
<=
'0'
;
pulse_cnt_invttlchdi_load_o
<=
'0'
;
pulse_cnt_rearch1o_load_o
<=
'0'
;
pulse_cnt_rearch1i_load_o
<=
'0'
;
pulse_cnt_rearch2o_load_o
<=
'0'
;
pulse_cnt_rearch2i_load_o
<=
'0'
;
pulse_cnt_rearch3o_load_o
<=
'0'
;
pulse_cnt_rearch3i_load_o
<=
'0'
;
pulse_cnt_rearch4o_load_o
<=
'0'
;
pulse_cnt_rearch4i_load_o
<=
'0'
;
pulse_cnt_rearch5o_load_o
<=
'0'
;
pulse_cnt_rearch5i_load_o
<=
'0'
;
pulse_cnt_rearch6o_load_o
<=
'0'
;
pulse_cnt_rearch16_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
4
downto
0
)
is
when
"00000"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch1o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch1o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch1o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00001"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch1i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch1i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch1i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00010"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch2o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch2o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch2o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00011"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch2i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch2i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch2i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00100"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch3o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch3o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch3o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00101"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch3i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch3i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch3i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00110"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch4o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch4o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch4o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"00111"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch4i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch4i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch4i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01000"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch5o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch5o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch5o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01001"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch5i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch5i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch5i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01010"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch6o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch6o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch6o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01011"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_ttlch6i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch6i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ttlch6i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01100"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchao_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch7o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchao
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01101"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchai_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch7i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchai
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01110"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchbo_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch8o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchbo
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01111"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchbi_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch8i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchbi
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10000"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchco_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch9o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchco
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10001"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchci_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch9i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchci
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10010"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchdo_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch10o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchdo
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10011"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_invttlchdi_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch10i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
invttlchdi
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10100"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch1o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch11o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch1o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10101"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch1i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch11i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch1i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10110"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch2o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch12o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch2o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10111"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch2i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch12i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch2i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11000"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch3o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch13o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch3o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11001"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch3i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch13i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch3i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11010"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch4o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch14o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch4o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11011"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch4i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch14i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch4i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11100"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch5o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch15o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch5o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11101"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch5i_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch15i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch5i
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11110"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch6o_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch16o_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch6o
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11111"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rearch16_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
ch16i_val
_i
;
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_
rearch16
_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
...
...
@@ -340,38 +532,70 @@ begin
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- Pulse counter value
pulse_cnt_ttlch1o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch1i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch2o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch2i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch3o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch3i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch4o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch4i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch5o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch5i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch6o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_ttlch6i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchao_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchai_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchbo_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchbi_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchco_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchci_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchdo_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_invttlchdi_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch1o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch1i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch2o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch2i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch3o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch3i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch4o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch4i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch5o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch5i_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch6o_o
<=
wrdata_reg
(
31
downto
0
);
-- Pulse counter value
pulse_cnt_rearch16_o
<=
wrdata_reg
(
31
downto
0
);
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
hdl/modules/pulse_cnt_wb.wb
View file @
5af5ba24
...
...
@@ -5,418 +5,451 @@ peripheral {
prefix = "pulse_cnt";
reg {
name = "CH1 output";
prefix = "ch1o";
name = "TTLCH1OCR";
prefix = "ttlch1o";
description = "TTL CH1 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH1 input";
prefix = "ch1i";
name = "TTLCH1ICR";
prefix = "ttlch1i";
description = "TTL CH1 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
name = "TTLCH2OCR";
prefix = "ttlch2o";
description = "TTL CH2 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
name = "TTLCH2ICR";
prefix = "ttlch2i";
description = "TTL CH2 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
name = "TTLCH3OCR";
prefix = "ttlch3o";
description = "TTL CH3 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
name = "TTLCH3ICR";
prefix = "ttlch3i";
description = "TTL CH3 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
name = "TTLCH4OCR";
prefix = "ttlch4o";
description = "TTL CH4 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
name = "TTLCH4ICR";
prefix = "ttlch4i";
description = "TTL CH4 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
name = "TTLCH5OCR";
prefix = "ttlch5o";
description = "TTL CH5 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
name = "TTLCH5ICR";
prefix = "ttlch5i";
description = "TTL CH5 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
name = "TTLCH6OCR";
prefix = "ttlch6o";
description = "TTL CH6 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
name = "TTLCH6ICR";
prefix = "ttlch6i";
description = "TTL CH6 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH7 output";
prefix = "ch7o";
name = "INVTTLCHAOCR";
prefix = "invttlchao";
description = "INV-TTL CHA output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH7 input";
prefix = "ch7i";
name = "INVTTLCHAICR";
prefix = "invttlchai";
description = "INV-TTL CHA input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH8 output";
prefix = "ch8o";
name = "INVTTLCHBOCR";
prefix = "invttlchbo";
description = "INV-TTL CHB output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH8 input";
prefix = "ch8i";
name = "INVTTLCHBICR";
prefix = "invttlchbi";
description = "INV-TTL CHB input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH9 output";
prefix = "ch9o";
name = "INVTTLCHCOCR";
prefix = "invttlchco";
description = "INV-TTL CHC output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH9 input";
prefix = "ch9i";
name = "INVTTLCHCICR";
prefix = "invttlchci";
description = "INV-TTL CHC input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH10 output";
prefix = "ch10o";
name = "INVTTLCHDOCR";
prefix = "invttlchdo";
description = "INV-TTL CHD output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH10 input";
prefix = "ch10i";
name = "INVTTLCHDICR";
prefix = "invttlchdi";
description = "INV-TTL CHD input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH11 output";
prefix = "ch11o";
name = "REARCH1OCR";
prefix = "rearch1o";
description = "Rear CH1 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH11 input";
prefix = "ch11i";
name = "REARCH1ICR";
prefix = "rearch1i";
description = "Rear CH1 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH12 output";
prefix = "ch12o";
name = "REARCH2OCR";
prefix = "rearch2o";
description = "Rear CH2 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH12 input";
prefix = "ch12i";
name = "REARCH2ICR";
prefix = "rearch2i";
description = "Rear CH2 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH13 output";
prefix = "ch13o";
name = "REARCH3OCR";
prefix = "rearch3o";
description = "Rear CH3 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH13 input";
prefix = "ch13i";
name = "REARCH3ICR";
prefix = "rearch3i";
description = "Rear CH3 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH14 output";
prefix = "ch14o";
name = "REARCH4OCR";
prefix = "rearch4o";
description = "Rear CH4 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH14 input";
prefix = "ch14i";
name = "REARCH4ICR";
prefix = "rearch4i";
description = "Rear CH4 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH15 output";
prefix = "ch15o";
name = "REARCH5OCR";
prefix = "rearch5o";
description = "Rear CH5 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH15 input";
prefix = "ch15i";
name = "REARCH5ICR";
prefix = "rearch5i";
description = "Rear CH5 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH16 output";
prefix = "ch16o";
name = "REARCH6OCR";
prefix = "rearch6o";
description = "Rear CH6 output counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH16 input";
prefix = "ch16i";
name = "REARCH6ICR";
prefix = "rearch16";
description = "Rear CH6 input counter register";
field {
name = "number of pulses";
prefix = "val";
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
hdl/modules/pulse_gen_gp.vhd
0 → 100644
View file @
5af5ba24
--==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
pulse_gen_gp
is
port
(
-- Input clock and active-low reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Active high enable signal
en_i
:
in
std_logic
;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
:
in
std_logic_vector
(
31
downto
0
);
pwidth_i
:
in
std_logic_vector
(
31
downto
0
);
freq_i
:
in
std_logic_vector
(
31
downto
0
);
-- Output pulse signal
pulse_o
:
out
std_logic
);
end
entity
pulse_gen_gp
;
architecture
behav
of
pulse_gen_gp
is
--============================================================================
-- Function and procedure declarations
--============================================================================
function
f_log2_size
(
A
:
natural
)
return
natural
is
begin
for
I
in
1
to
64
loop
-- Works for up to 64 bits
if
(
2
**
I
>=
A
)
then
return
(
I
);
end
if
;
end
loop
;
return
(
63
);
end
function
f_log2_size
;
--============================================================================
-- Signal declarations
--============================================================================
signal
delay_int
:
unsigned
(
31
downto
0
);
signal
pwidth_int
:
unsigned
(
31
downto
0
);
signal
freq_int
:
unsigned
(
31
downto
0
);
signal
pulse_cnt
:
unsigned
(
31
downto
0
);
signal
delay_cnt
:
unsigned
(
31
downto
0
);
signal
delay_en
:
std_logic
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
delay_int
<=
unsigned
(
delay_i
);
pwidth_int
<=
unsigned
(
pwidth_i
);
freq_int
<=
unsigned
(
freq_i
);
--============================================================================
-- Delay logic
--============================================================================
p_delay
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
or
(
en_i
=
'0'
)
then
delay_en
<=
'1'
;
delay_cnt
<=
(
others
=>
'0'
);
else
if
(
delay_int
=
(
delay_int
'range
=>
'0'
))
then
delay_en
<=
'0'
;
elsif
(
delay_en
=
'1'
)
then
delay_cnt
<=
delay_cnt
+
1
;
if
(
delay_cnt
=
delay_int
)
then
delay_en
<=
'0'
;
delay_cnt
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
if
;
end
process
p_delay
;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
or
(
en_i
=
'0'
)
then
pulse_cnt
<=
(
others
=>
'0'
);
pulse_o
<=
'0'
;
elsif
(
delay_en
=
'0'
)
then
pulse_cnt
<=
pulse_cnt
+
1
;
pulse_o
<=
'0'
;
if
(
pulse_cnt
<
pwidth_int
)
then
pulse_o
<=
'1'
;
elsif
(
pulse_cnt
=
freq_int
-1
)
then
pulse_cnt
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
process
p_gen_pulse
;
end
architecture
behav
;
--==============================================================================
-- architecture end
--==============================================================================
hdl/syn/pts.xise
View file @
5af5ba24
...
...
@@ -340,7 +340,7 @@
<file
xil_pn:name=
"../top/pts.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
<file
xil_pn:name=
"../
top/pts
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../
ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg
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xil_pn:type=
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>
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xil_pn:name=
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/>
</file>
<file
xil_pn:name=
"../modules/pts_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -355,372 +355,375 @@
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xil_pn:name=
"../modules/clk_info_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
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>
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>
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c.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"120"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/
platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/
modules/wishbone/wb_vic/wb_slave_vic
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"121"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/x
wb_xilinx_fpga_loader
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/x
loader_registers_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"122"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
x
wb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"123"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
xloader_wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
wb_xilinx_fpga_loader
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"124"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil
_multiboot/spi_master
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil
inx_fpga_loader/xloader_wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"125"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/
multiboot_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/
spi_master
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"126"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_
regs
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_
fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"127"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/
xwb_xil_multiboot
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/
multiboot_regs
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"128"
/>
</file>
<file
xil_pn:name=
"../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"129"
/>
</file>
</files>
<bindings/>
...
...
hdl/top/pts.vhd
View file @
5af5ba24
...
...
@@ -142,6 +142,9 @@ architecture arch of pts is
--============================================================================
-- Type declarations
--============================================================================
-- Pulse counter register and load value types
type
t_pcr
is
array
(
15
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_pcr_ldval
is
array
(
15
downto
0
)
of
std_logic_vector
(
31
downto
0
);
--============================================================================
-- Constant declarations
...
...
@@ -150,7 +153,7 @@ architecture arch of pts is
constant
c_board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54343835"
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
1
1
;
-- slave order definitions
constant
c_slv_pts_regs
:
natural
:
=
0
;
...
...
@@ -194,33 +197,33 @@ architecture arch of pts is
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_pts_regs
=>
c_addr_pts_regs
--
c_slv_onewire_mst => c_addr_onewire_mst,
--
c_slv_dac_spi_125 => c_addr_dac_spi_125,
--
c_slv_clk_info_125 => c_addr_clk_info_125,
--
c_slv_dac_spi_20 => c_addr_dac_spi_20,
--
c_slv_clk_info_20 => c_addr_clk_info_20,
--
c_slv_sfp_i2c => c_addr_sfp_i2c,
--
c_slv_endpoint => c_addr_endpoint,
--
c_slv_minic => c_addr_minic,
--
c_slv_dpram => c_addr_dpram,
--
c_slv_pulse_cntrs => c_addr_pulse_cntrs
c_slv_pts_regs
=>
c_addr_pts_regs
,
c_slv_onewire_mst
=>
c_addr_onewire_mst
,
c_slv_dac_spi_125
=>
c_addr_dac_spi_125
,
c_slv_clk_info_125
=>
c_addr_clk_info_125
,
c_slv_dac_spi_20
=>
c_addr_dac_spi_20
,
c_slv_clk_info_20
=>
c_addr_clk_info_20
,
c_slv_sfp_i2c
=>
c_addr_sfp_i2c
,
c_slv_endpoint
=>
c_addr_endpoint
,
c_slv_minic
=>
c_addr_minic
,
c_slv_dpram
=>
c_addr_dpram
,
c_slv_pulse_cntrs
=>
c_addr_pulse_cntrs
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_pts_regs
=>
c_mask_pts_regs
--
c_slv_onewire_mst => c_mask_onewire_mst,
--
c_slv_dac_spi_125 => c_mask_dac_spi_125,
--
c_slv_clk_info_125 => c_mask_clk_info_125,
--
c_slv_dac_spi_20 => c_mask_dac_spi_20,
--
c_slv_clk_info_20 => c_mask_clk_info_20,
--
c_slv_sfp_i2c => c_mask_sfp_i2c,
--
c_slv_endpoint => c_mask_endpoint,
--
c_slv_minic => c_mask_minic,
--
c_slv_dpram => c_mask_dpram,
--
c_slv_pulse_cntrs => c_mask_pulse_cntrs
c_slv_pts_regs
=>
c_mask_pts_regs
,
c_slv_onewire_mst
=>
c_mask_onewire_mst
,
c_slv_dac_spi_125
=>
c_mask_dac_spi_125
,
c_slv_clk_info_125
=>
c_mask_clk_info_125
,
c_slv_dac_spi_20
=>
c_mask_dac_spi_20
,
c_slv_clk_info_20
=>
c_mask_clk_info_20
,
c_slv_sfp_i2c
=>
c_mask_sfp_i2c
,
c_slv_endpoint
=>
c_mask_endpoint
,
c_slv_minic
=>
c_mask_minic
,
c_slv_dpram
=>
c_mask_dpram
,
c_slv_pulse_cntrs
=>
c_mask_pulse_cntrs
);
-- MiniNIC log2 of memory size
...
...
@@ -274,6 +277,171 @@ architecture arch of pts is
);
end
component
pts_regs
;
-- General-purpose pulse generator
component
pulse_gen_gp
is
port
(
-- Input clock and active-low reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Active high enable signal
en_i
:
in
std_logic
;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
:
in
std_logic_vector
(
31
downto
0
);
pwidth_i
:
in
std_logic_vector
(
31
downto
0
);
freq_i
:
in
std_logic_vector
(
31
downto
0
);
-- Output pulse signal
pulse_o
:
out
std_logic
);
end
component
pulse_gen_gp
;
component
pulse_cnt_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1OCR'
pulse_cnt_ttlch1o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1ICR'
pulse_cnt_ttlch1i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch1i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2OCR'
pulse_cnt_ttlch2o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2ICR'
pulse_cnt_ttlch2i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch2i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3OCR'
pulse_cnt_ttlch3o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3ICR'
pulse_cnt_ttlch3i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch3i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4OCR'
pulse_cnt_ttlch4o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4ICR'
pulse_cnt_ttlch4i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch4i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5OCR'
pulse_cnt_ttlch5o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5ICR'
pulse_cnt_ttlch5i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch5i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6OCR'
pulse_cnt_ttlch6o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6ICR'
pulse_cnt_ttlch6i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_ttlch6i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAOCR'
pulse_cnt_invttlchao_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchao_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchao_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAICR'
pulse_cnt_invttlchai_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchai_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchai_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBOCR'
pulse_cnt_invttlchbo_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbo_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbo_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBICR'
pulse_cnt_invttlchbi_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbi_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchbi_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCOCR'
pulse_cnt_invttlchco_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchco_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchco_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCICR'
pulse_cnt_invttlchci_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchci_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchci_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDOCR'
pulse_cnt_invttlchdo_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdo_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdo_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDICR'
pulse_cnt_invttlchdi_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdi_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_invttlchdi_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1OCR'
pulse_cnt_rearch1o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1ICR'
pulse_cnt_rearch1i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch1i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2OCR'
pulse_cnt_rearch2o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2ICR'
pulse_cnt_rearch2i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch2i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3OCR'
pulse_cnt_rearch3o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3ICR'
pulse_cnt_rearch3i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch3i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4OCR'
pulse_cnt_rearch4o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4ICR'
pulse_cnt_rearch4i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch4i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5OCR'
pulse_cnt_rearch5o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5ICR'
pulse_cnt_rearch5i_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5i_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch5i_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6OCR'
pulse_cnt_rearch6o_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch6o_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch6o_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
pulse_cnt_rearch16_o
:
out
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch16_i
:
in
std_logic_vector
(
31
downto
0
);
pulse_cnt_rearch16_load_o
:
out
std_logic
);
end
component
pulse_cnt_wb
;
--============================================================================
-- Signal declarations
--============================================================================
...
...
@@ -317,6 +485,23 @@ architecture arch of pts is
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
switches
:
std_logic_vector
(
7
downto
0
);
-- TTL pulse test signals
signal
ttl_pulse_en
:
std_logic
;
signal
ttl_trigs_a
:
std_logic_vector
(
9
downto
0
);
signal
ttl_trigs
:
std_logic_vector
(
9
downto
0
);
signal
ttl_trigs_redge_p
:
std_logic_vector
(
9
downto
0
);
signal
ttl_pulses
:
std_logic_vector
(
9
downto
0
);
signal
ttl_pulses_d0
:
std_logic_vector
(
9
downto
0
);
signal
ttl_pulses_redge_p
:
std_logic_vector
(
9
downto
0
);
-- Pulse counter register signals
signal
ipcr_ld
:
std_logic_vector
(
15
downto
0
);
signal
ipcr_ldval
:
t_pcr_ldval
;
signal
ipcr
:
t_pcr
;
signal
opcr_ld
:
std_logic_vector
(
15
downto
0
);
signal
opcr_ldval
:
t_pcr_ldval
;
signal
opcr
:
t_pcr
;
--==============================================================================
-- architecture begin
--==============================================================================
...
...
@@ -477,7 +662,7 @@ begin
pts_csr_front_led_en_o
=>
pulse_led_en
,
pts_csr_rear_led_en_o
=>
open
,
pts_csr_stat_led_en_o
=>
stat_led_en
,
pts_csr_ttl_en_o
=>
op
en
,
pts_csr_ttl_en_o
=>
ttl_pulse_
en
,
pts_csr_blo_en_o
=>
open
,
pts_csr_blo_led_o
=>
open
,
pts_csr_rst_o
=>
rst_fr_reg
,
...
...
@@ -491,6 +676,247 @@ begin
pts_csr_i2c_wdto_load_o
=>
i2c_wdto_bit_rst_ld
);
--============================================================================
-- TTL pulse test logic
--============================================================================
-- Channel enable outputs
global_oen_o
<=
'1'
;
ttl_oen_o
<=
ttl_pulse_en
;
inv_oen_o
<=
ttl_pulse_en
;
-- First, instantiate a general-purpose pulse generator to generate the output
-- pulse from CH1 to CH2
--
-- 1-us pulses are generated twice a second.
cmp_first_pulse_gen
:
pulse_gen_gp
port
map
(
-- Input clock and active-low reset
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
-- Active high enable signal
en_i
=>
ttl_pulse_en
,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
=>
x"00000000"
,
pwidth_i
=>
x"00000014"
,
freq_i
=>
x"00989680"
,
-- Output pulse signal
pulse_o
=>
ttl_pulses
(
0
)
);
-- Assign the trigger inputs to internal signals
ttl_trigs_a
(
5
downto
0
)
<=
not
ttl_n_i
;
ttl_trigs_a
(
9
downto
6
)
<=
not
inv_n_i
;
-- Synchronize these triggers in the 20-MHz clock domain
gen_ttl_sync_chains
:
for
i
in
0
to
9
generate
cmp_ttl_sync_chain
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
data_i
=>
ttl_trigs_a
(
i
),
synced_o
=>
ttl_trigs
(
i
),
ppulse_o
=>
ttl_trigs_redge_p
(
i
)
);
end
generate
gen_ttl_sync_chains
;
-- Now, generate nine pulse generator blocks connected to the TTL outputs
-- and with the TTL inputs as triggers.
--
-- External to the FPGA, the inputs of CH2 are expected to be connected to CH1,
-- which generates pulses for the daisy-chain, then CH2 outputs to CH3, CH3 to
-- CH4 and so on, until the last INV_TTL output, which is expected to
-- be connected back to the input of CH1.
--
-- The pulse generator is configured for fixed-width pulses of 1us.
gen_ttl_pulse_gens
:
for
i
in
1
to
9
generate
cmp_pulse_gens
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
true
,
g_pwidth
=>
20
,
g_duty_cycle_div
=>
5
)
port
map
(
clk_i
=>
clk_20_i
,
rst_n_i
=>
rst_20_n
,
gf_en_n_i
=>
'1'
,
en_i
=>
ttl_pulse_en
,
trig_a_i
=>
ttl_trigs
(
i
),
pulse_err_p_o
=>
open
,
pulse_o
=>
ttl_pulses
(
i
)
);
end
generate
gen_ttl_pulse_gens
;
-- Assign the FPGA outputs for the TTL channels
ttl_o
<=
ttl_pulses
(
5
downto
0
);
inv_o
<=
ttl_pulses
(
9
downto
6
);
-- Implement the pulse counter registers for the TTL channels
gen_ttl_pulse_cntrs
:
for
i
in
0
to
9
generate
-- First, some rising-edge detectors for output pulses
p_ttl_pulse_redge
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
ttl_pulses_d0
(
i
)
<=
'0'
;
ttl_pulses_redge_p
(
i
)
<=
'0'
;
else
ttl_pulses_d0
(
i
)
<=
ttl_pulses
(
i
);
ttl_pulses_redge_p
(
i
)
<=
ttl_pulses
(
i
)
and
(
not
ttl_pulses_d0
(
i
));
end
if
;
end
if
;
end
process
p_ttl_pulse_redge
;
-- Now, the actual I/O pulse counters
p_ttl_pulse_cnt
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
opcr
(
i
)
<=
(
others
=>
'0'
);
ipcr
(
i
)
<=
(
others
=>
'0'
);
else
if
(
opcr_ld
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
unsigned
(
opcr_ldval
(
i
));
elsif
(
ttl_pulses_redge_p
(
i
)
=
'1'
)
then
opcr
(
i
)
<=
opcr
(
i
)
+
1
;
end
if
;
if
(
ipcr_ld
(
i
)
=
'1'
)
then
ipcr
(
i
)
<=
unsigned
(
ipcr_ldval
(
i
));
elsif
(
ttl_trigs_redge_p
(
i
)
=
'1'
)
then
ipcr
(
i
)
<=
ipcr
(
i
)
+
1
;
end
if
;
end
if
;
end
if
;
end
process
p_ttl_pulse_cnt
;
end
generate
gen_ttl_pulse_cntrs
;
--============================================================================
-- Pulse counter registers, retaining values for pulse counters of both RS-485
-- and TTL pulse repetition tests.
--============================================================================
cmp_pulse_cnt_regs
:
pulse_cnt_wb
port
map
(
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
adr
(
6
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_pulse_cntrs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_pulse_cntrs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_pulse_cntrs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_pulse_cntrs
)
.
stall
,
pulse_cnt_ttlch1o_o
=>
opcr_ldval
(
0
),
pulse_cnt_ttlch1o_i
=>
std_logic_vector
(
opcr
(
0
)),
pulse_cnt_ttlch1o_load_o
=>
opcr_ld
(
0
),
pulse_cnt_ttlch1i_o
=>
ipcr_ldval
(
0
),
pulse_cnt_ttlch1i_i
=>
std_logic_vector
(
ipcr
(
0
)),
pulse_cnt_ttlch1i_load_o
=>
ipcr_ld
(
0
),
pulse_cnt_ttlch2o_o
=>
opcr_ldval
(
1
),
pulse_cnt_ttlch2o_i
=>
std_logic_vector
(
opcr
(
1
)),
pulse_cnt_ttlch2o_load_o
=>
opcr_ld
(
1
),
pulse_cnt_ttlch2i_o
=>
ipcr_ldval
(
1
),
pulse_cnt_ttlch2i_i
=>
std_logic_vector
(
ipcr
(
1
)),
pulse_cnt_ttlch2i_load_o
=>
ipcr_ld
(
1
),
pulse_cnt_ttlch3o_o
=>
opcr_ldval
(
2
),
pulse_cnt_ttlch3o_i
=>
std_logic_vector
(
opcr
(
2
)),
pulse_cnt_ttlch3o_load_o
=>
opcr_ld
(
2
),
pulse_cnt_ttlch3i_o
=>
ipcr_ldval
(
2
),
pulse_cnt_ttlch3i_i
=>
std_logic_vector
(
ipcr
(
2
)),
pulse_cnt_ttlch3i_load_o
=>
ipcr_ld
(
2
),
pulse_cnt_ttlch4o_o
=>
opcr_ldval
(
3
),
pulse_cnt_ttlch4o_i
=>
std_logic_vector
(
opcr
(
3
)),
pulse_cnt_ttlch4o_load_o
=>
opcr_ld
(
3
),
pulse_cnt_ttlch4i_o
=>
ipcr_ldval
(
3
),
pulse_cnt_ttlch4i_i
=>
std_logic_vector
(
ipcr
(
3
)),
pulse_cnt_ttlch4i_load_o
=>
ipcr_ld
(
3
),
pulse_cnt_ttlch5o_o
=>
opcr_ldval
(
4
),
pulse_cnt_ttlch5o_i
=>
std_logic_vector
(
opcr
(
4
)),
pulse_cnt_ttlch5o_load_o
=>
opcr_ld
(
4
),
pulse_cnt_ttlch5i_o
=>
ipcr_ldval
(
4
),
pulse_cnt_ttlch5i_i
=>
std_logic_vector
(
ipcr
(
4
)),
pulse_cnt_ttlch5i_load_o
=>
ipcr_ld
(
4
),
pulse_cnt_ttlch6o_o
=>
opcr_ldval
(
5
),
pulse_cnt_ttlch6o_i
=>
std_logic_vector
(
opcr
(
5
)),
pulse_cnt_ttlch6o_load_o
=>
opcr_ld
(
5
),
pulse_cnt_ttlch6i_o
=>
ipcr_ldval
(
5
),
pulse_cnt_ttlch6i_i
=>
std_logic_vector
(
ipcr
(
5
)),
pulse_cnt_ttlch6i_load_o
=>
ipcr_ld
(
5
),
pulse_cnt_invttlchao_o
=>
opcr_ldval
(
6
),
pulse_cnt_invttlchao_i
=>
std_logic_vector
(
opcr
(
6
)),
pulse_cnt_invttlchao_load_o
=>
opcr_ld
(
6
),
pulse_cnt_invttlchai_o
=>
ipcr_ldval
(
6
),
pulse_cnt_invttlchai_i
=>
std_logic_vector
(
ipcr
(
6
)),
pulse_cnt_invttlchai_load_o
=>
ipcr_ld
(
6
),
pulse_cnt_invttlchbo_o
=>
opcr_ldval
(
7
),
pulse_cnt_invttlchbo_i
=>
std_logic_vector
(
opcr
(
7
)),
pulse_cnt_invttlchbo_load_o
=>
opcr_ld
(
7
),
pulse_cnt_invttlchbi_o
=>
ipcr_ldval
(
7
),
pulse_cnt_invttlchbi_i
=>
std_logic_vector
(
ipcr
(
7
)),
pulse_cnt_invttlchbi_load_o
=>
ipcr_ld
(
7
),
pulse_cnt_invttlchco_o
=>
opcr_ldval
(
8
),
pulse_cnt_invttlchco_i
=>
std_logic_vector
(
opcr
(
8
)),
pulse_cnt_invttlchco_load_o
=>
opcr_ld
(
8
),
pulse_cnt_invttlchci_o
=>
ipcr_ldval
(
8
),
pulse_cnt_invttlchci_i
=>
std_logic_vector
(
ipcr
(
8
)),
pulse_cnt_invttlchci_load_o
=>
ipcr_ld
(
8
),
pulse_cnt_invttlchdo_o
=>
opcr_ldval
(
9
),
pulse_cnt_invttlchdo_i
=>
std_logic_vector
(
opcr
(
9
)),
pulse_cnt_invttlchdo_load_o
=>
opcr_ld
(
9
),
pulse_cnt_invttlchdi_o
=>
ipcr_ldval
(
9
),
pulse_cnt_invttlchdi_i
=>
std_logic_vector
(
ipcr
(
9
)),
pulse_cnt_invttlchdi_load_o
=>
ipcr_ld
(
9
),
pulse_cnt_rearch1o_o
=>
opcr_ldval
(
10
),
pulse_cnt_rearch1o_i
=>
std_logic_vector
(
opcr
(
10
)),
pulse_cnt_rearch1o_load_o
=>
opcr_ld
(
10
),
pulse_cnt_rearch1i_o
=>
ipcr_ldval
(
10
),
pulse_cnt_rearch1i_i
=>
std_logic_vector
(
ipcr
(
10
)),
pulse_cnt_rearch1i_load_o
=>
ipcr_ld
(
10
),
pulse_cnt_rearch2o_o
=>
opcr_ldval
(
11
),
pulse_cnt_rearch2o_i
=>
std_logic_vector
(
opcr
(
11
)),
pulse_cnt_rearch2o_load_o
=>
opcr_ld
(
11
),
pulse_cnt_rearch2i_o
=>
ipcr_ldval
(
11
),
pulse_cnt_rearch2i_i
=>
std_logic_vector
(
ipcr
(
11
)),
pulse_cnt_rearch2i_load_o
=>
ipcr_ld
(
11
),
pulse_cnt_rearch3o_o
=>
opcr_ldval
(
12
),
pulse_cnt_rearch3o_i
=>
std_logic_vector
(
opcr
(
12
)),
pulse_cnt_rearch3o_load_o
=>
opcr_ld
(
12
),
pulse_cnt_rearch3i_o
=>
ipcr_ldval
(
12
),
pulse_cnt_rearch3i_i
=>
std_logic_vector
(
ipcr
(
12
)),
pulse_cnt_rearch3i_load_o
=>
ipcr_ld
(
12
),
pulse_cnt_rearch4o_o
=>
opcr_ldval
(
13
),
pulse_cnt_rearch4o_i
=>
std_logic_vector
(
opcr
(
13
)),
pulse_cnt_rearch4o_load_o
=>
opcr_ld
(
13
),
pulse_cnt_rearch4i_o
=>
ipcr_ldval
(
13
),
pulse_cnt_rearch4i_i
=>
std_logic_vector
(
ipcr
(
13
)),
pulse_cnt_rearch4i_load_o
=>
ipcr_ld
(
13
),
pulse_cnt_rearch5o_o
=>
opcr_ldval
(
14
),
pulse_cnt_rearch5o_i
=>
std_logic_vector
(
opcr
(
14
)),
pulse_cnt_rearch5o_load_o
=>
opcr_ld
(
14
),
pulse_cnt_rearch5i_o
=>
ipcr_ldval
(
14
),
pulse_cnt_rearch5i_i
=>
std_logic_vector
(
ipcr
(
14
)),
pulse_cnt_rearch5i_load_o
=>
ipcr_ld
(
14
),
pulse_cnt_rearch6o_o
=>
opcr_ldval
(
15
),
pulse_cnt_rearch6o_i
=>
std_logic_vector
(
opcr
(
15
)),
pulse_cnt_rearch6o_load_o
=>
opcr_ld
(
15
),
pulse_cnt_rearch16_o
=>
ipcr_ldval
(
15
),
pulse_cnt_rearch16_i
=>
std_logic_vector
(
ipcr
(
15
)),
pulse_cnt_rearch16_load_o
=>
ipcr_ld
(
15
)
);
--============================================================================
-- LED test logic
-- * test bicolor LEDs and its driving circuit (IC1)
...
...
@@ -649,17 +1075,11 @@ begin
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
ttl_o
<=
(
others
=>
'0'
);
inv_o
<=
(
others
=>
'0'
);
rs485_o
<=
(
others
=>
'1'
);
flash_cs_n_o
<=
'1'
;
flash_mosi_o
<=
'0'
;
flash_sclk_o
<=
'0'
;
-- Channel enable
global_oen_o
<=
'0'
;
ttl_oen_o
<=
'0'
;
inv_oen_o
<=
'0'
;
rs485_oen_o
<=
'0'
;
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
...
...
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