Gateware releases
Release gateware use the MultiBoot feature implemented on Xilinx Spartan-6 FPGAs. This means that there are two bitstreams on the CONV-TTL-BLO flash chips, a golden version and (normally) a latest release version.
Preparing a bitstream containing the golden bitstream for MultiBoot
To prepare a bitstream containing both the golden and the release bitstream for download directly to the flash using, e.g. Xilinx iMPACT, use the catbstream.py script, which can be found under the software/* folder of the CONV-TTL-BLO repository:
git clone git:https://www.ohwr.org/level-conversion/conv-ttl-blo.git
cd conv-ttl-blo/software/catbstream
Gateware version
The gateware version number can be read from the GWVERS field of the status register (SR) at address 0x4 for all gatewares. The GWVERS field (SR[7:0]) is defined as follows:
- SR[7:4] gateware version major number (e.g., 1.0, 2.0, 3.0, ..., 15.0)
- SR[3:0] gateware version minor number (e.g., 1.0, 1.1, 1.2, ..., 1.15)
Some possible values for the gateware version major number:
- 0 -- denotes golden gateware (v0.0, v0.1, etc.), the fallback bitstream in case of MultiBoot error
- 1/2/3/etc. -- major releases of the application bistream after MultiBoot success
Golden gateware
Version | Date | Information |
0.0 | 06-01-2015 | Golden bitstream for fallback in case of MultiBoot error |
Release gateware
Version | Date | Information |
1.0 | 06-01-2015 | Release bitstream with pulse pass-through and diagnostics support |
Theodor-Adrian Stana, Jan. 2014