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Conv TTL RS485 - Gateware
Commit cc0052b6 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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THIS COMMIT IS A HACK USED FOR TESTING. it switches in the UCF file some input… 

THIS COMMIT IS A HACK USED FOR TESTING. it switches in the UCF file some input and output pulse pins to allow for testing of optical repeater and map 1 optical channel to two TTL channels. DO NOT USE THIS BRANCH FOR PRODUCTION OR ANY OTHER PURPOSES. BRANCH WILL BE DELETED IF NO FURTHER TESTS ARE REQUIRED
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conv-common-gw @ 28160cad
Subproject commit b2dc909805306fa5ac1ea0e732162558833ac4f1 Subproject commit 28160cad7c141a3bfa1d9b90d3a80c911364a725
syn/Release/conv_ttl_rs485.xise
View file @ cc0052b6
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and --> <!-- along with the project source files, is sufficient to open and -->
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...@@ -19,6 +19,9 @@ ...@@ -19,6 +19,9 @@
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...@@ -339,381 +344,405 @@ ...@@ -339,381 +344,405 @@
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</files> </files>
<bindings/> <bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project> </project>
top/conv_ttl_rs485.ucf
View file @ cc0052b6
...@@ -182,10 +182,10 @@ NET "pcbrev_i[5]" IOSTANDARD = LVCMOS33; ...@@ -182,10 +182,10 @@ NET "pcbrev_i[5]" IOSTANDARD = LVCMOS33;
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
# RS-485 I/O (fs = failsafe) # RS-485 I/O (fs = failsafe)
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
NET "rs485_n_i[1]" LOC = Y12; NET "rs485_n_i[0]" LOC = Y12;
NET "rs485_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[0]" LOC = AB12;
NET "rs485_n_i[0]" IOSTANDARD = LVCMOS33; NET "rs485_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[1]" LOC = AB12;
NET "rs485_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[2]" LOC = AB11; NET "rs485_n_i[2]" LOC = AB11;
NET "rs485_n_i[2]" IOSTANDARD = LVCMOS33; NET "rs485_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[3]" LOC = AB10; NET "rs485_n_i[3]" LOC = AB10;
...@@ -195,10 +195,10 @@ NET "rs485_n_i[4]" IOSTANDARD = LVCMOS33; ...@@ -195,10 +195,10 @@ NET "rs485_n_i[4]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[5]" LOC = AA8; NET "rs485_n_i[5]" LOC = AA8;
NET "rs485_n_i[5]" IOSTANDARD = LVCMOS33; NET "rs485_n_i[5]" IOSTANDARD = LVCMOS33;
NET "rs485_o[0]" LOC = W18; NET "rs485_o[1]" LOC = W18;
NET "rs485_o[0]" IOSTANDARD = LVCMOS33;
NET "rs485_o[1]" LOC = Y18;
NET "rs485_o[1]" IOSTANDARD = LVCMOS33; NET "rs485_o[1]" IOSTANDARD = LVCMOS33;
NET "rs485_o[0]" LOC = Y18;
NET "rs485_o[0]" IOSTANDARD = LVCMOS33;
NET "rs485_o[2]" LOC = W17; NET "rs485_o[2]" LOC = W17;
NET "rs485_o[2]" IOSTANDARD = LVCMOS33; NET "rs485_o[2]" IOSTANDARD = LVCMOS33;
NET "rs485_o[3]" LOC = Y17; NET "rs485_o[3]" LOC = Y17;
...@@ -208,10 +208,10 @@ NET "rs485_o[4]" IOSTANDARD = LVCMOS33; ...@@ -208,10 +208,10 @@ NET "rs485_o[4]" IOSTANDARD = LVCMOS33;
NET "rs485_o[5]" LOC = Y15; NET "rs485_o[5]" LOC = Y15;
NET "rs485_o[5]" IOSTANDARD = LVCMOS33; NET "rs485_o[5]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[1]" LOC = AA12; NET "rs485_fs_n_i[0]" LOC = AA12;
NET "rs485_fs_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[0]" LOC = Y11;
NET "rs485_fs_n_i[0]" IOSTANDARD = LVCMOS33; NET "rs485_fs_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[1]" LOC = Y11;
NET "rs485_fs_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[2]" LOC = Y10; NET "rs485_fs_n_i[2]" LOC = Y10;
NET "rs485_fs_n_i[2]" IOSTANDARD = LVCMOS33; NET "rs485_fs_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[3]" LOC = AA10; NET "rs485_fs_n_i[3]" LOC = AA10;
...@@ -237,10 +237,10 @@ NET "iterm_en_o[4]" IOSTANDARD = LVCMOS33; ...@@ -237,10 +237,10 @@ NET "iterm_en_o[4]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[5]" LOC = W9; NET "iterm_en_o[5]" LOC = W9;
NET "iterm_en_o[5]" IOSTANDARD = LVCMOS33; NET "iterm_en_o[5]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[0]" LOC = T22; NET "oterm_en_o[1]" LOC = T22;
NET "oterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[1]" LOC = T21;
NET "oterm_en_o[1]" IOSTANDARD = LVCMOS33; NET "oterm_en_o[1]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[0]" LOC = T21;
NET "oterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[2]" LOC = T20; NET "oterm_en_o[2]" LOC = T20;
NET "oterm_en_o[2]" IOSTANDARD = LVCMOS33; NET "oterm_en_o[2]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[3]" LOC = U20; NET "oterm_en_o[3]" LOC = U20;
...@@ -253,10 +253,10 @@ NET "oterm_en_o[5]" IOSTANDARD = LVCMOS33; ...@@ -253,10 +253,10 @@ NET "oterm_en_o[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Channel LEDs # Channel LEDs
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
NET "led_rear_n_o[0]" LOC = AB17; NET "led_rear_n_o[1]" LOC = AB17;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[1]" LOC = AB19;
NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33; NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[0]" LOC = AB19;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[2]" LOC = AA16; NET "led_rear_n_o[2]" LOC = AA16;
NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33; NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[3]" LOC = AA18; NET "led_rear_n_o[3]" LOC = AA18;
......
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