Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL RS485 - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL RS485 - Gateware
Commits
c1ebffb5
Commit
c1ebffb5
authored
Feb 06, 2018
by
Evangelia Gousiou
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
WIP test bench
parent
fadf5f25
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
199 additions
and
83 deletions
+199
-83
print_pkg.vhd
sim/print_pkg.vhd
+2
-1
testbench.vhd
sim/testbench.vhd
+108
-60
testbench_pkg.vhd
sim/testbench_pkg.vhd
+89
-22
No files found.
sim/print_pkg.vhd
View file @
c1ebffb5
...
...
@@ -616,7 +616,8 @@ PACKAGE BODY print_pkg IS
WRITELINE
(
output
,
l
);
END
print_now_s_std
;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE
print_now_s_std_s_std
(
s1
:
IN
string
;
vec1
:
IN
std_logic_vector
;
s2
:
IN
string
;
vec2
:
IN
std_logic_vector
)
IS
...
...
sim/testbench.vhd
View file @
c1ebffb5
...
...
@@ -68,8 +68,8 @@ architecture behav of testbench is
signal
gf_en_n_in
:
std_logic
;
signal
ttl_n_in
,
ttl_out
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
rs485_n_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
ttl_n_in
,
ttl_out
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
signal
rs485_n_in
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
-- signal sscl_in : std_logic;
-- signal ssda_in : std_logic;
...
...
@@ -91,33 +91,37 @@ architecture behav of testbench is
signal
rtmm_in
:
std_logic_vector
(
2
downto
0
);
signal
rtmp_in
:
std_logic_vector
(
2
downto
0
);
signal
line_front_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
line_inv_in
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
line_rear_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
line_front_fs_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
line_inv_fs_in
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
line_rear_fs_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
line_front_in
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
signal
line_inv_in
:
std_logic_vector
(
C_NR_INV_CHANS
-1
downto
0
);
signal
line_rear_in
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
signal
line_front_fs_in
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
signal
line_inv_fs_in
:
std_logic_vector
(
C_NR_INV_CHANS
-1
downto
0
);
signal
line_rear_fs_in
:
std_logic_vector
(
C_NR_CHANS
-1
downto
0
);
signal
i2c_master_rcvd_val
,
i2c_master_rcvd_val1
,
i2c_master_rcvd_val2
,
i2c_master_rcvd_val3
,
i2c_master_rcvd_val4
:
std_logic_vector
(
31
downto
0
);
signal
i2c_master_rcvd_val_str
:
string
(
1
to
8
);
signal
i2c_m_in
:
t_i2c_master_in
;
signal
i2c_m_out
:
t_i2c_master_out
;
signal
mscl
,
msda
:
std_logic_vector
(
c_nr_masters
-1
downto
0
);
signal
sscl
,
ssda
:
std_logic_vector
(
c_nr_slaves
-1
downto
0
);
signal
mscl
,
msda
:
std_logic_vector
(
C_NR_MASTERS
-1
downto
0
);
signal
sscl
,
ssda
:
std_logic_vector
(
C_NR_SLAVES
-1
downto
0
);
signal
scl
,
sda
:
std_logic
;
---
signal
buf_byte_cnt
,
nb_pulses_to_send
:
natural
;
signal
buf_byte_cnt
:
natural
;
-- signal nb_pulses_to_send_slv : std_logic_vector(31 downto 0);
signal
reg_id
:
integer
:
=
0
;
signal
adr
:
std_logic_vector
(
31
downto
0
);
procedure
read_i2c
(
signal
i2c_m_in
:
out
t_i2c_master_in
;
signal
i2c_m_out
:
in
t_i2c_master_out
;
procedure
read_i2c
(
signal
i2c_m_in
:
out
t_i2c_master_in
;
signal
i2c_m_out
:
in
t_i2c_master_out
;
constant
slv_addr
:
in
std_logic_vector
(
6
downto
0
);
constant
reg_addr
:
in
std_logic_vector
(
31
downto
0
);
signal
rcvd_val
:
out
std_logic_vector
(
31
downto
0
))
is
constant
reg_name
:
string
(
1
to
8
);
signal
rcvd_val
:
out
std_logic_vector
(
31
downto
0
);
constant
exp_val
:
in
std_logic_vector
(
31
downto
0
))
is
begin
print_now
(
"-------------------------------------------------"
);
print_now
(
"read_i2c: start"
);
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_slv_addr
<=
"1011110"
;
...
...
@@ -128,20 +132,26 @@ architecture behav of testbench is
i2c_m_in
.
i2c_master_reg_addr
<=
reg_addr
;
i2c_m_in
.
i2c_master_start
<=
'1'
;
i2c_m_in
.
i2c_master_rdwr
<=
'1'
;
--0: write
wait
for
c_clk_20_per
;
wait
for
C_CLK_20_PER
;
i2c_m_in
.
i2c_master_start
<=
'0'
;
wait
until
i2c_m_out
.
i2c_master_finish
=
'1'
;
rcvd_val
<=
i2c_m_out
.
i2c_master_rcvd_val
;
print_now_s_std_s_std
(
"
------->
I2C value read from 0x"
,
reg_addr
(
7
downto
0
),
print_now_s_std_s_std
(
"I2C value read from 0x"
,
reg_addr
(
7
downto
0
),
" is 0x"
,
i2c_m_out
.
i2c_master_rcvd_val
);
wait
until
i2c_m_out
.
i2c_master_finish
=
'0'
;
print_now
(
"read_i2c: completed"
);
if
i2c_m_out
.
i2c_master_rcvd_val
=
exp_val
then
print_now_s_s
(
"[OK] Correct reading from reg "
,
reg_name
,
"; expected value matches read value"
);
else
print_now_s_std_s_std
(
"-------> [ERR]: Read value"
,
i2c_master_rcvd_val
,
" expected value "
,
exp_val
);
end
if
;
print_now
(
"-------------------------------------------------"
);
end
procedure
read_i2c
;
--==============================================================================
-- architecture begin
--==============================================================================
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
...
...
@@ -162,41 +172,33 @@ begin
sda_i
=>
sda
,
sda_o
=>
ssda_out
,
sda_en_o
=>
ssda_en_out
,
-- VME interface
vme_sysreset_n_i
=>
vme_sysreset_n
,
vme_ga_i
=>
"11110"
,
--
vme_gap_i
=>
'0'
,
-- PCB version recognition
pcbrev_i
=>
pcbrev
,
-- Channel enable
global_oen_o
=>
open
,
ttl_oen_o
=>
open
,
inv_oen_o
=>
open
,
rs485_oen_o
=>
open
,
-- Front panel channels
ttl_n_i
=>
ttl_n_in
,
--: in std_logic_vector(5 downto 0);
ttl_o
=>
ttl_out
,
--: out std_logic_vector(5 downto 0);
inv_n_i
=>
(
others
=>
'0'
),
--inv_n_in, --: in std_logic_vector(3 downto 0);
inv_o
=>
open
,
--inv_n_out, --: out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i
=>
rs485_n_in
,
--: in std_logic_vector(5 downto 0);
rs485_fs_n_i
=>
(
others
=>
'0'
),
--: in std_logic_vector(5 downto 0); --failsafe?
rs485_o
=>
open
,
--: out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o
=>
open
,
oterm_en_o
=>
open
,
-- Channel leds
led_front_n_o
=>
open
,
led_front_inv_n_o
=>
open
,
led_rear_n_o
=>
open
,
-- SPI interface to on-board flash chip
flash_cs_n_o
=>
open
,
flash_sclk_o
=>
open
,
...
...
@@ -217,18 +219,14 @@ begin
sfp_scl_b
=>
open
,
sfp_tx_disable_o
=>
open
,
sfp_tx_fault_i
=>
'1'
,
-- Thermometer data port
thermometer_b
=>
open
,
-- Switches
sw_gp_n_i
=>
sw_gp_n_in
,
sw_multicast_n_i
=>
(
others
=>
'0'
),
-- not used
-- RTM lines
rtmm_i
=>
rtmm_in
,
rtmp_i
=>
rtmp_in
,
-- Front panel bicolor LEDs
led_ctrl0_o
=>
open
,
led_ctrl0_oen_o
=>
open
,
...
...
@@ -252,17 +250,17 @@ begin
p_clk_20
:
process
begin
clk_20
<=
'0'
;
wait
for
c_clk_20_per
/
2
;
wait
for
C_CLK_20_PER
/
2
;
clk_20
<=
'1'
;
wait
for
c_clk_20_per
/
2
;
wait
for
C_CLK_20_PER
/
2
;
end
process
;
p_clk_125
:
process
begin
clk_125
<=
'0'
;
wait
for
c_clk_125_per
/
2
;
wait
for
C_CLK_125_PER
/
2
;
clk_125
<=
'1'
;
wait
for
c_clk_125_per
/
2
;
wait
for
C_CLK_125_PER
/
2
;
end
process
;
clk_125_p
<=
clk_125
;
...
...
@@ -310,13 +308,13 @@ begin
mscl
(
0
)
<=
mscl_out
when
(
mscl_en_out
=
'0'
)
else
'1'
;
msda
(
0
)
<=
msda_out
when
(
msda_en_out
=
'0'
)
else
'1'
;
--
----------------------------------------------------------------------------
-- Bus model
instantiation and
connection to master and slaves
--
----------------------------------------------------------------------------
--
============================================================================
-- Bus model connection to master and slaves
--
============================================================================
cmp_i2c_bus
:
entity
work
.
i2c_bus_model
generic
map
(
g_nr_masters
=>
c_nr_masters
,
g_nr_slaves
=>
c_nr_slaves
g_nr_masters
=>
C_NR_MASTERS
,
g_nr_slaves
=>
C_NR_SLAVES
)
port
map
(
mscl_i
=>
mscl
,
...
...
@@ -333,27 +331,77 @@ begin
--i2c access
p_stim_i2c
:
process
variable
i
:
integer
:
=
0
;
variable
nb_pulses_to_send
:
integer
:
=
150
;
variable
nb_pulses_to_send_slv
:
std_logic_vector
(
31
downto
0
);
begin
nb_pulses_to_send
<=
250
;
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_slv_addr
<=
"1011110"
;
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
print
(
"***************************************************"
)
;
print
(
" Start of Tests"
)
;
print
(
"***************************************************"
);
---------------------------------------------------------------------------
-- VME reset
print_now
(
"Sending VME reset"
);
wait
until
vme_sysreset_n
=
'1'
;
print_now
(
"VME reset completed"
);
wait
for
6500
ns
;
-- for resets and inhibit_pulse to have finished
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- I2C reading of the board ID register
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
0
)
.
reg_addr
,
c_REG_MAP
(
0
)
.
reg_name
,
i2c_master_rcvd_val
,
C_BOARD_ID
);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Sending pulses to Front Panel Channel 1
nb_pulses_to_send_slv
:
=
std_logic_vector
(
to_unsigned
(
nb_pulses_to_send
,
nb_pulses_to_send_slv
'length
));
print_now_s_i
(
"Sending TTL front pulses to Channel 1: "
,
nb_pulses_to_send
);
generate_pulse
(
ttl_n_in
(
0
),
nb_pulses_to_send
,
200
ns
,
200
ns
);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Reading from the I2C Front Panel regs; read only first 2 Channels to speed up testbench
while
not
(
i
=
3
)
loop
if
i
=
0
then
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
4
)
.
reg_addr
,
c_REG_MAP
(
i
+
4
)
.
reg_name
,
i2c_master_rcvd_val
,
nb_pulses_to_send_slv
);
else
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
4
)
.
reg_addr
,
c_REG_MAP
(
i
+
4
)
.
reg_name
,
i2c_master_rcvd_val
,
(
others
=>
'0'
));
end
if
;
i
:
=
i
+
1
;
end
loop
;
---------------------------------------------------------------------------
-- Reading from the I2C Rear Panel regs; read only first 2 Channels to speed up testbench
i
:
=
0
;
while
not
(
i
=
3
)
loop
if
i
=
0
then
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
10
)
.
reg_addr
,
c_REG_MAP
(
i
+
10
)
.
reg_name
,
i2c_master_rcvd_val
,
(
others
=>
'0'
));
else
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
10
)
.
reg_addr
,
c_REG_MAP
(
i
+
10
)
.
reg_name
,
i2c_master_rcvd_val
,
(
others
=>
'0'
));
end
if
;
i
:
=
i
+
1
;
end
loop
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Sending 150 more pulses to Front Panel Channel 1, to make the counter roll
print_now_s_i
(
"Sending TTL front pulses to Channel 1: "
,
nb_pulses_to_send
);
generate_pulse
(
ttl_n_in
(
0
),
nb_pulses_to_send
,
200
ns
,
200
ns
);
---------------------------------------------------------------------------
-- Reading from the I2C Front Panel regs; read one reg read to speed up testbench
i
:
=
0
;
while
not
(
i
=
2
)
loop
if
i
=
0
then
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
4
)
.
reg_addr
,
c_REG_MAP
(
i
+
4
)
.
reg_name
,
i2c_master_rcvd_val
,
nb_pulses_to_send_slv
);
else
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
c_REG_MAP
(
i
+
4
)
.
reg_addr
,
c_REG_MAP
(
i
+
4
)
.
reg_name
,
i2c_master_rcvd_val
,
(
others
=>
'0'
));
end
if
;
i
:
=
i
+
1
;
end
loop
;
wait
for
6
us
;
-- for resets and inhibit_pulse to have finished
print_now_s_i
(
"Sending pulses: "
,
nb_pulses_to_send
);
generate_pulses
(
ttl_n_in
,
nb_pulses_to_send
,
100
ns
,
100
ns
);
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
x"0000_0000"
,
i2c_master_rcvd_val
);
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
x"0000_0010"
,
i2c_master_rcvd_val
);
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
x"0000_0014"
,
i2c_master_rcvd_val
);
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
x"0000_0018"
,
i2c_master_rcvd_val
);
read_i2c
(
i2c_m_in
,
i2c_m_out
,
"1011110"
,
x"0000_0000"
,
i2c_master_rcvd_val
);
end
process
p_stim_i2c
;
...
...
sim/testbench_pkg.vhd
View file @
c1ebffb5
...
...
@@ -33,20 +33,84 @@ package testbench_pkg is
--============================================================================
-- Clock periods
constant
c_clk_20_per
:
time
:
=
50
ns
;
constant
c_clk_125_per
:
time
:
=
8
ns
;
constant
c_reset_width
:
time
:
=
200
ns
;
constant
C_CLK_20_PER
:
time
:
=
50
ns
;
constant
C_CLK_125_PER
:
time
:
=
8
ns
;
constant
C_RESET_WIDTH
:
time
:
=
200
ns
;
-- DUT configuration (generics):
constant
c_nr_chans
:
integer
:
=
6
;
constant
c_nr_inv_chans
:
integer
:
=
4
;
constant
c_board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
constant
c_gwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"40"
;
constant
C_NR_CHANS
:
integer
:
=
6
;
constant
C_NR_INV_CHANS
:
integer
:
=
4
;
constant
C_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"54343835"
;
-- Number of I2C masters and slaves for the I2C bus model
constant
c_nr_masters
:
positive
:
=
1
;
constant
c_nr_slaves
:
positive
:
=
1
;
constant
C_NR_MASTERS
:
positive
:
=
1
;
constant
C_NR_SLAVES
:
positive
:
=
1
;
-- DUT register map:
constant
C_BIDR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
constant
C_SR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000004"
;
constant
C_ERR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000008"
;
constant
C_CR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000000C"
;
constant
C_CH1FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000010"
;
constant
C_CH2FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000014"
;
constant
C_CH3FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000018"
;
constant
C_CH4FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000001C"
;
constant
C_CH5FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000020"
;
constant
C_CH6FPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000024"
;
constant
C_CH1RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000028"
;
constant
C_CH2RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000002C"
;
constant
C_CH3RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000030"
;
constant
C_CH4RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000034"
;
constant
C_CH5RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000038"
;
constant
C_CH6RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000003C"
;
type
t_reg
is
record
reg_addr
:
std_logic_vector
(
31
downto
0
);
reg_name
:
string
(
1
to
8
);
end
record
;
type
t_reg_table
is
array
(
natural
range
<>
)
of
t_reg
;
constant
c_REG_MAP
:
t_reg_table
(
15
downto
0
)
:
=
(
0
=>
(
reg_addr
=>
C_BIDR
,
reg_name
=>
"BIDR "
),
1
=>
(
reg_addr
=>
C_SR
,
reg_name
=>
"SR "
),
2
=>
(
reg_addr
=>
C_ERR
,
reg_name
=>
"ERR "
),
3
=>
(
reg_addr
=>
C_CR
,
reg_name
=>
"CR "
),
4
=>
(
reg_addr
=>
C_CH1FPPCR
,
reg_name
=>
"CH1FPPCR"
),
5
=>
(
reg_addr
=>
C_CH2FPPCR
,
reg_name
=>
"CH3FPPCR"
),
6
=>
(
reg_addr
=>
C_CH3FPPCR
,
reg_name
=>
"CH3FPPCR"
),
7
=>
(
reg_addr
=>
C_CH4FPPCR
,
reg_name
=>
"CH4FPPCR"
),
8
=>
(
reg_addr
=>
C_CH5FPPCR
,
reg_name
=>
"CH5FPPCR"
),
9
=>
(
reg_addr
=>
C_CH6FPPCR
,
reg_name
=>
"CH6FPPCR"
),
10
=>
(
reg_addr
=>
C_CH1RPPCR
,
reg_name
=>
"CH1RPPCR"
),
11
=>
(
reg_addr
=>
C_CH2RPPCR
,
reg_name
=>
"CH3RPPCR"
),
12
=>
(
reg_addr
=>
C_CH3RPPCR
,
reg_name
=>
"CH3RPPCR"
),
13
=>
(
reg_addr
=>
C_CH4RPPCR
,
reg_name
=>
"CH4RPPCR"
),
14
=>
(
reg_addr
=>
C_CH5RPPCR
,
reg_name
=>
"CH5RPPCR"
),
15
=>
(
reg_addr
=>
C_CH6RPPCR
,
reg_name
=>
"CH6RPPCR"
));
--============================================================================
-- Types declarations
...
...
@@ -176,10 +240,10 @@ end component conv_ttl_rs485;
-- signal rcvd_val : out std_logic_vector(31 downto 0));
procedure
generate_pulse
s
(
signal
pulses_n_out
:
out
std_logic_vector
(
c_nr_chans
-1
downto
0
)
;
nb_of_pulses
:
in
natural
;
ns_on
:
in
time
;
ns_off
:
in
time
);
procedure
generate_pulse
(
signal
pulse_n_out
:
out
std_logic
;
nb_of_pulses
:
in
natural
;
ns_on
:
in
time
;
ns_off
:
in
time
);
end
testbench_pkg
;
package
body
testbench_pkg
is
...
...
@@ -200,23 +264,26 @@ package body testbench_pkg is
end
procedure
;
----------------------------------------------------------------------------------------------------
procedure
generate_pulse
s
(
signal
pulses_n_out
:
out
std_logic_vector
(
c_nr_chans
-1
downto
0
)
;
nb_of_pulses
:
in
natural
;
ns_on
:
in
time
;
ns_off
:
in
time
)
is
procedure
generate_pulse
(
signal
pulse_n_out
:
out
std_logic
;
nb_of_pulses
:
in
natural
;
ns_on
:
in
time
;
ns_off
:
in
time
)
is
variable
numb_cnt
:
natural
;
begin
numb_cnt
:
=
0
;
while
not
(
numb_cnt
=
nb_of_pulses
)
loop
pulse
s_n_out
<=
(
others
=>
'1'
)
;
wait
for
ns_off
;
--min period is 240us??
pulse
s_n_out
<=
(
others
=>
'0'
)
;
pulse
_n_out
<=
'1'
;
wait
for
ns_off
;
pulse
_n_out
<=
'0'
;
wait
for
ns_on
;
pulse
s_n_out
<=
(
others
=>
'1'
)
;
pulse
_n_out
<=
'1'
;
numb_cnt
:
=
numb_cnt
+
1
;
end
loop
;
end
procedure
generate_pulses
;
end
procedure
generate_pulse
;
end
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment