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C
Conv TTL RS485 - Gateware
Commit 3395277e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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[submodule "ip_cores/conv-common-gw"]
path = ip_cores/conv-common-gw
url = git://ohwr.org/level-conversion/conv-common-gw.git
doc/gw-test-procedure/Makefile 0 → 100644
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FILE=gw-test-procedure
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/gw-test-procedure/README.txt 0 → 100644
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Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape
\ No newline at end of file
doc/gw-test-procedure/cern-title.tex 0 → 100644
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\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\Large \textbf{CONV-TTL-RS485 Gateware Test Procedure}}
\noindent \rule{\textwidth}{.1cm}
\hfill December 16, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/gw-test-procedure/fig/Makefile 0 → 100644
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SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
doc/gw-test-procedure/fig/cern-logo.svg 0 → 100644
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<?xml version="1.0" encoding="utf-8"?>
<!-- Generator: Adobe Illustrator 15.0.2, SVG Export Plug-In . SVG Version: 6.00 Build 0) -->
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
width="184.252px" height="184.252px" viewBox="0 0 184.252 184.252" enable-background="new 0 0 184.252 184.252"
xml:space="preserve">
<g>
<path fill="#0053A1" d="M38.544,76.536c-0.921,0.7-4.123,2.692-8.941,2.692c-8.718,0-14.658-5.495-14.658-13.872
c0-8.328,6.298-13.87,14.862-13.87c3.332,0,7.147,1.026,9.275,1.939c-0.445,0.985-0.811,2.286-0.965,3.1l-0.233,0.077
c-1.647-1.823-4.295-3.402-8.213-3.402c-4.972,0-10.696,4.027-10.696,12.056c0,7.819,5.832,11.974,11.046,11.974
c4.684,0,6.927-2.186,8.939-3.885l0.154,0.154L38.544,76.536z"/>
<path fill="#0053A1" d="M60.139,77.312c0-0.588,0.05-1.193,0.092-1.487c-2.644,0.243-9.903,0.463-12.734,0.504
c-0.048-0.707-0.11-9.091-0.04-10.387c1.132,0,7.114,0.078,9.787,0.35c-0.077-0.388-0.116-0.962-0.116-1.35
c0-0.387,0.039-1.082,0.116-1.469c-2.286,0.193-5.214,0.387-9.787,0.387c0-0.969,0.079-8.037,0.118-9.701
c5.036,0,9.596,0.313,12.148,0.504c-0.042-0.264-0.092-0.807-0.092-1.337c0-0.528,0.035-0.958,0.092-1.322
c-1.342,0.09-5.678,0.195-8.003,0.195c-2.324,0-5.913-0.078-8.237-0.195c0.154,3.294,0.311,6.664,0.311,9.997v6.664
c0,3.333-0.156,6.704-0.311,10.075c2.363-0.117,5.99-0.194,8.354-0.194c0.111,0,0.227,0,0.343,0
c0.81,0.003,1.835,0.014,2.893,0.033c1.833,0.034,3.767,0.089,5.159,0.161l0,0l0,0C60.173,78.331,60.139,77.899,60.139,77.312z"/>
<path fill="#0053A1" d="M68.815,65.622v3.082c0,3.332,0.154,6.701,0.311,10.034c-0.66-0.117-1.852-0.128-2.096-0.128
c-0.243,0-1.435,0.012-2.094,0.128c0.155-3.333,0.31-6.703,0.31-10.034v-6.666c0-3.332-0.155-6.703-0.31-10.035
c1.473,0.117,3.336,0.195,4.809,0.195c1.473,0,2.945-0.195,4.417-0.195c4.379,0,8.39,1.293,8.39,6.169
c0,5.161-5.14,7.013-8.085,7.401c1.899,2.363,8.7,10.646,10.947,13.165c-0.774-0.117-2.073-0.128-2.427-0.128
c-0.354,0-1.691,0.012-2.427,0.128c-1.531-2.335-6.437-9.686-9.77-13.117C70.688,65.621,68.815,65.622,68.815,65.622z
M71.411,64.204c3.199-0.065,7.4-1.081,7.4-5.502c0-3.852-3.371-5.076-6.005-5.076c-1.782,0-2.945,0.116-3.758,0.193
c-0.117,2.829-0.232,5.428-0.232,8.218c0,0,0,1.851,0,2.131C69.2,64.221,71.016,64.21,71.411,64.204z"/>
<path fill="#0053A1" d="M112.594,51.99c-0.453,0.078-1.013,0.142-1.699,0.142c-0.676,0-1.257-0.073-1.651-0.142
c0.17,3.174,0.462,9.047,0.462,12.899c0,2.898,0,5.428-0.04,6.862c-1.409-1.499-17.576-18.23-19.219-20.016l-1.269-0.013
c0.057,2.465,0.129,5.141,0.129,10.022c0,6.249-0.087,12.896-0.406,16.994c0.453-0.079,1.012-0.142,1.698-0.142
c0.677,0,1.257,0.071,1.65,0.142c-0.169-3.173-0.461-9.048-0.461-12.898c0-2.899,0.002-5.882,0.041-7.314
c1.409,1.5,17.667,18.458,19.218,20.561l1.269,0.012c-0.058-2.465-0.129-5.234-0.129-10.116
C112.187,62.734,112.275,56.085,112.594,51.99z"/>
<path fill="#0053A1" d="M42.069,121.789c-7.614-12.048-9.781-23.679-10.084-32.58c-1.173,0-2.346,0-3.519,0
c0.295,9.71,2.65,19.893,7.919,29.872C37.627,120.083,40.544,121.358,42.069,121.789z"/>
<path fill="#0053A1" d="M184.25,1.679c0,0-87.554-0.694-115.47-0.679c-4.369,0.003-7.302,0.311-8.248,0.371
C26.048,3.605,0.115,33.842,0,66.817c-0.032,9.586,2.522,20.39,6.667,34.973c5.476,19.267,11.891,41.367,11.891,41.367h3.499
L9.128,99.539l0.097-0.065c9.497,18.347,31.392,33.086,56.237,33.086c13.407,0,25.841-3.753,35.638-10.666l0.085,0.08
l-57.516,61.204h4.492c0,0,40.387-42.968,54.125-57.556c10.527-11.178,15.996-18.381,18.285-22.119
c2.625-4.287,10.964-16.645,10.652-34.847l0.112-0.008l25.203,114.529h3.618c0,0-21.146-93.744-25.25-113.349
c-4.038-19.292-8.809-31.258-13.957-38.083c-1.769-0.985-4.527-2.107-5.828-2.411c7.472,9.428,13.055,23.454,13.055,37.489
c0,34.355-27.95,62.304-62.306,62.304c-34.354,0-62.304-27.949-62.304-62.304c0-34.356,28.05-62.306,62.324-62.306
c15.235,0,29.356,5.588,40.209,14.79c2.098,0.29,4.91,0.945,6.589,1.551l0.013-0.035C104.902,13.046,95.163,7.265,84.33,4.225
c0-0.084,0-0.089,0-0.089l99.922,0.623L184.25,1.679z"/>
<path fill="#0053A1" d="M50.808,132.873c-2.228-0.329-5.011-1.118-6.685-1.836c7.5,8.536,17.82,15.366,27.953,19.198l2.659-2.821
C63.744,143.702,55.756,137.737,50.808,132.873"/>
<path fill="#0053A1" d="M142.469,127.885c-11.121,13.615-28.388,22.783-48.226,22.771c-4.259-0.001-8.391-0.478-11.836-1.179
l-2.847,3.022c5.445,1.258,10.271,1.731,14.885,1.731c20.405,0,37.861-9.523,48.972-22.057L142.469,127.885"/>
<path fill="#0053A1" d="M165.644,17.304l-6.001,61.965h-0.113c-0.851-11.696-6.682-25.666-13.883-34.498
c-12.5-15.329-30.842-24.585-51.444-24.585c-19.647,0-37.15,8.717-49.192,22.381l2.758,2.186
C59.145,31.888,75.442,23.643,94.2,23.643c22.836,0,41.439,11.704,51.845,27.615c9.286,14.197,12.365,32.39,10.213,45.719
c-0.727,4.502-2.36,13.257-8.359,23.176l1.05,4.614c7.358-11.405,11.091-21.556,14.005-47.503
c2.234-19.906,6.073-59.962,6.073-59.962L165.644,17.304z"/>
</g>
</svg>
doc/gw-test-procedure/fig/ohwr-logo.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with sK1/UniConvertor (http://sk1project.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="595.276pt"
height="841.89pt"
viewBox="0 0 595.276 841.89"
fill-rule="evenodd"
id="svg2"
version="1.1"
inkscape:version="0.47pre4 r22446"
sodipodi:docname="ohr_logo.svg"
inkscape:export-filename="/home/kikito/Desktop/ohr_logo.png"
inkscape:export-xdpi="126.50246"
inkscape:export-ydpi="126.50246">
<metadata
id="metadata280">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<sodipodi:namedview
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1"
objecttolerance="10"
gridtolerance="10"
guidetolerance="10"
inkscape:pageopacity="0"
inkscape:pageshadow="2"
inkscape:window-width="1440"
inkscape:window-height="850"
id="namedview278"
showgrid="false"
inkscape:zoom="0.63429547"
inkscape:cx="154.33516"
inkscape:cy="531.90964"
inkscape:window-x="0"
inkscape:window-y="25"
inkscape:window-maximized="1"
inkscape:current-layer="svg2" />
<defs
id="defs4">
<inkscape:perspective
sodipodi:type="inkscape:persp3d"
inkscape:vp_x="0 : 526.18127 : 1"
inkscape:vp_y="0 : 1000 : 0"
inkscape:vp_z="744.09497 : 526.18127 : 1"
inkscape:persp3d-origin="372.04749 : 350.78752 : 1"
id="perspective282" />
<marker
id="ArrowEnd"
viewBox="0 0 10 10"
refX="0"
refY="5"
markerUnits="strokeWidth"
markerWidth="4"
markerHeight="3"
orient="auto">
<path
d="M 0 0 L 10 5 L 0 10 z"
id="path7" />
</marker>
<marker
id="ArrowStart"
viewBox="0 0 10 10"
refX="10"
refY="5"
markerUnits="strokeWidth"
markerWidth="4"
markerHeight="3"
orient="auto">
<path
d="M 10 0 L 0 5 L 10 10 z"
id="path10" />
</marker>
</defs>
<g
id="g3499"
inkscape:export-xdpi="90"
inkscape:export-ydpi="90">
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 107.755,514.353 c -5.661,-12.668 -2.428,-72.033 27.045,-123.394 22.747,-41.806 31.009,-41.861 72.045,-90.603 8.161,-9.826 9.689,-34.606 8.637,-75.755 -1.802,-55.035 14.078,-78.473 27.341,-89.73 5.865,-4.977 10.547,-7.841 14.105,-9.545 37.228,-21.361 78.903,-14.392 104.265,-5.733 3.859,1.407 7.059,3.561 10.358,5.884 21.543,15.169 31.746,47.617 30.424,75.788 -1.411,33.732 -4.26,62.909 5.092,72.584 34.4,32.294 52.584,62.536 67.218,89.578 3.994,7.378 15.965,32.437 19.234,42.973 5.74,21.891 1.526,58.494 -2.018,74.667 3.554,2.424 9.949,8.448 15.019,12.008 13.194,8.326 33.776,16.462 32.95,23.841 -0.392,5.225 -37.929,59.66 -53.917,85.024 -21.622,32.656 -52.625,70.038 -55.664,72.853 -3.51,3.063 -9.044,4.89 -13.678,5.142 -1.665,0.221 -12.546,-3.138 -25.919,-5.724 -12.175,-2.353 -27.482,-4.546 -37.974,-6.055 -5.657,-1.888 -9.645,-11.663 -13.22,-11.761 -7.337,0.199 -23.69,-3.125 -39.484,1.401 -12.9,1.922 -15.965,1.621 -30.255,0.569 -5.256,-1.29 -5.352,-3.138 -7.073,-1.194 -6.908,11.395 -15.781,25.698 -31.42,35.82 -0.768,0.734 -4.275,-0.045 -5.75,-0.609 -35.648,-13.625 -41.715,-6.383 -98.64,-30.944 -14.633,-5.781 -37.7825,-15.278 -49.3237,-18.371 -2.6059,-0.699 -4.0742,-3.158 -5.1835,-3.826 -1.5764,-0.893 -4.3026,-1.048 -5.8114,-1.619 -14.5759,-5.507 -16.3689,-17.271 -15.4357,-19.91 2.4742,-11.348 4.645,-17.421 8.1421,-26.956 11.29,-31.507 26.0679,-51.947 41.5342,-73.392 0.821,-2.451 8.543,-1.378 7.357,-3.011 z"
id="path18" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 225.082,191.519 c 0.121,-1.355 1.131,-3.089 1.944,-2.949 15.396,2.651 26.629,0.066 59.797,-3.31 2.052,-0.409 2.566,1.596 2.759,2.472 2.918,13.25 3.328,24.422 6.093,39.511 0.856,4.578 0.139,5.131 -2.364,6.529 -32.127,9.828 -43.471,22.124 -62.592,33.738 -1.62,0.985 -5.331,3.049 -4.775,-0.453 -1.669,-26.851 -3.398,-48.647 -0.862,-75.538 z"
id="path20" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 333.076,304.867 c 9.991,-7.049 16.336,-13.305 27.018,-18.674 2.198,-1.059 7.122,-10.116 4.789,-12.047 -1.975,-2.075 -2.534,-3.341 -1.611,-8.126 0.243,-3.622 0.569,-6.371 -1.059,-9.728 -0.327,-0.456 -1.283,-3.711 -6.181,-1.053 -0.559,0.664 -1.314,0.462 -2.03,0.062 -14.772,-7.373 -30.275,-18.78 -48.385,-21.397 -1.872,-0.464 -2.519,-2.224 -3.073,-5.382 -3.054,-17.195 -2.474,-31.38 -4.845,-48.302 -0.559,-1.931 -4.503,-5.359 -8.967,-3.97 -8.342,3.599 -33.849,7.498 -59.109,6.906 -1.951,-0.482 -4.344,0.319 -3.668,-3.667 4.56,-19.272 3.716,-21.915 23.916,-41.891 38.35,-31.721 111.302,-22.676 122.21,28.926 4.099,17.731 6.568,60.64 -0.597,95.909 -0.535,4.698 -0.96,9.285 1.697,13.51 14.242,20.576 31.349,34.56 49.562,50.885 13.271,10.635 46.231,49.613 53.953,91.5 2.585,14.518 4.455,30.965 1.328,50.454 -0.132,0.397 -0.205,1.137 -2.053,0.154 -11.715,-8.161 -24.455,-10.028 -33.638,-10.147 -3.193,-0.041 -3.118,-1.618 -3.069,-2.293 0.19,-8.567 0.634,-17.304 -0.71,-26.727 -1.472,-10.045 -7.148,-28.792 -22.716,-46.376 -2.106,-2.485 -5.204,-5.277 -11.335,-3.988 -3.5,0.875 -4.048,3.815 -3.399,6.44 4.357,15.671 12.446,28.859 13.381,51.226 -7.064,-11.201 -18.334,-24.119 -27.112,-34.54 -17.041,-17.015 -16.463,-18.441 -34.309,-28.444 -3.039,-1.305 -6.802,-2.296 -9.149,-3.601 -3.123,-1.595 -2.713,-5.43 -3.268,-8.007 -2.854,-18.884 -5.307,-33.003 -8.291,-52.254 -0.307,-1.31 -1.162,-4.158 0.72,-5.358 z"
id="path22" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 67.4257,623.695 c 14.0267,-54.464 33.2903,-66.747 53.8463,-100.062 3.215,-4.014 1.522,-3.582 -2.511,-2.086 -5.854,2.173 -6.889,-1.95 -14.409,4.888 -7.4603,6.783 -15.8039,22.053 -19.9727,28.661 -9.7038,17.012 -14.6677,27.543 -20.0041,41.488 -6.9562,16.113 -9.1531,29.193 0.1743,31.341 1.5424,0.356 1.6372,1.249 2.8762,-4.23 z"
id="path24" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 223.509,595.27 c -13.932,-13.931 -32.698,-29.305 -47.886,-42.114 -8.165,-6.888 -21.045,-17.267 -27.499,-21.995 -18.706,-13.703 -21.209,-2.344 -30.422,10.561 l -11.92,16.696 c -7.6585,10.727 -22.7348,34.92 -25.9552,48.128 -2.3658,9.701 -10.6312,22.228 1.2886,28.027 9.4062,7.588 84.6446,34.736 106.6496,39.513 11.865,2.575 18.951,3.877 32.241,5.558 17.233,2.178 35.505,-26.493 42.145,-40.268 2.876,-5.965 -13.753,-15.829 -19.215,-23.306 -4.071,-5.574 -10.48,-10.882 -19.427,-20.8 z"
id="path26" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 91.5647,634.558 c -5.6582,-1.042 -8.1074,-3.19 -5.071,-8.372 3.0365,-5.181 6.9497,-13.176 13.1321,-26.58 0.9912,-2.15 2.4962,-4.954 8.1122,-1.001 5.264,3.705 14.206,11.15 23.836,18.209 0.641,0.47 3.066,2.718 -0.2,5.912 -4.087,7.218 -3.667,9.693 -6.093,17.386 -0.826,2.608 -2.897,4.115 -7.694,1.658 -4.798,-2.458 -20.3641,-6.171 -26.0223,-7.212 z"
id="path28" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 98.4522,629.527 c -3.6944,-0.655 -5.2936,-2.007 -3.3111,-5.268 1.9826,-3.261 4.5377,-8.293 8.5749,-16.728 0.647,-1.353 1.629,-3.118 5.296,-0.63 3.437,2.332 9.276,7.017 15.563,11.459 0.419,0.296 2.002,1.711 -0.13,3.721 -2.669,4.543 -2.394,6.1 -3.978,10.942 -0.539,1.641 -1.892,2.589 -5.024,1.043 -3.133,-1.547 -13.296,-3.884 -16.9908,-4.539 z"
id="path30" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 118.049,512.132 c -6.71,-7.445 -4.264,-29.25 -1.675,-47.94 20.578,-86.046 46.603,-106.942 95.483,-155.85 3.43,-3.144 6.805,-7.069 8.245,-11.954 1.776,-7.094 3.648,-20.767 5.968,-20.269 1.864,0 0.258,-0.325 2.883,0.109 2.603,0.286 -0.65,10.661 1.519,12.574 13.994,16.271 21.91,15.299 21.877,20.208 0.408,3.182 1.738,5.733 2.239,8.476 3.564,19.524 5.688,27.751 4.23,52.557 -0.602,5.044 -2.255,4.757 -3.664,5.796 -58.282,33.955 -68.512,78.379 -73.274,111.967 -8.011,-20.073 -6.951,-48.693 4.648,-86.257 0.338,-1.404 1.468,-3.073 2.506,-4.626 4.041,-5.663 -5.011,-12.076 -9.578,-5.663 -22.607,30.029 -29.279,61.28 -26.173,89.267 5.306,26.262 25.034,47.115 45.364,63.161 22.097,18.25 22.908,20.754 32.341,31.399 3.523,5.861 -5.768,13.103 -8.58,9.324 -29.863,-26.796 -56.24,-50.309 -88.084,-71.842 -1.026,-0.694 -2.06,-1.566 -3.989,-1.601 -4.273,0.745 -11.574,2.68 -12.286,1.164 z"
id="path32" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 294.009,327.753 c -1.609,18.521 -0.105,37.527 0.784,56.518 -12.151,2.445 -17.594,3.373 -27.457,7.085 -29.188,11.01 -40.509,24.793 -58.915,57.059 -10.405,25.766 -9,47.682 -11.124,83.234 -16.858,-11.595 -31.971,-34.75 -34.987,-48.805 -6.692,-29.607 6.75,-60.493 13.951,-74.531 -10.621,45.371 -9.071,64.266 0.711,88.674 2.647,4.413 8.193,8.083 11.997,5.919 2.893,-2.325 1.066,-11.209 1.786,-16.433 2.259,-45.762 29.602,-87.782 71.207,-103.815 6.742,-2.585 5.147,-1.917 5.374,-6.61 0.149,-18.388 0.127,-38.509 -5.155,-59.272 -3.027,-8.71 3.938,-3.501 7.573,-1.505 7.889,4.217 16.366,9.336 24.255,12.482 z"
id="path34" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 281.418,342.075 c -0.264,0.183 -0.527,0.365 -0.785,0.549 2.375,0.039 4.638,0.587 6.344,2.638 3.824,4.6 1.742,13.093 -5.134,12.885 -6.152,-0.186 -10.642,-6.552 -8.384,-12.419 0.747,-1.941 2.36,-3.768 4.483,-4.207 1.184,-0.245 2.313,0.223 3.476,0.554 z"
id="path36" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 281.559,362.52 c -0.226,0.669 -0.476,1.329 -0.724,1.987 3.878,1.176 7.422,3.962 6.477,8.55 -1.155,5.613 -11.374,8.345 -12.671,1.49 -0.648,-3.425 0.41,-7.248 2.744,-9.682 -0.192,-0.154 -0.368,-0.298 -0.52,-0.432 l 0.114,-0.572 c 0.452,0.014 0.92,0.052 1.397,0.115 0.921,-0.704 1.988,-1.214 3.183,-1.456 z"
id="path38" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 273.868,321.819 0.141,-0.368 c 3.157,-0.576 6.555,-0.64 8.874,2.055 3.738,4.345 0.107,13.443 -6.128,11.501 -3.959,-1.234 -8.424,-6.332 -6.277,-10.661 0.81,-1.631 1.995,-2.285 3.39,-2.527 z"
id="path40" />
<path
style="fill:none;stroke:#ff0000;stroke-width:0.500094"
d="m 278.38,329.04 0.026,-0.005 0.013,-0.013 0.006,-0.01 -0.045,0.028 z"
id="path42" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 300.096,326.255 c -0.385,12.457 -0.139,31.878 0.96,38.269 0.427,10.884 0.924,14.981 0.816,18.582 23.806,-3.953 38.885,-1.19 48.696,4.928 16.884,12.628 26.771,23.593 35.84,36.456 4.21,5.795 13.99,28.362 12.441,39.189 8.105,-3.923 19.249,-5.798 30.426,-5.624 1.062,-5.425 7.014,-35.772 -15.674,-64.863 4.968,17.92 10.255,38.332 8.207,57.236 -1.459,4.571 -8.977,5.332 -10.679,1.368 -3.449,-13.224 -2.686,-12.062 -8.768,-20.253 -13.258,-17.709 -24.737,-32.038 -41.375,-44.589 -5.815,-4.631 -7.212,-6.602 -21.212,-11.028 -2.009,-1.067 -9.561,-0.335 -7.148,-8.174 2.079,-7.055 -4.121,-33.797 -6.799,-52.945 -0.077,-7.553 -7.015,-0.787 -8.086,-0.386 -7.15,5.028 -17.499,11.106 -17.645,11.834 z"
id="path44" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 368.464,479.697 c 1.592,3.184 6.129,4.788 9.693,5.893 1.866,0.579 4.908,-2.632 8.083,-2.58 3.487,0.057 1.86,-1.873 1.86,-4.87 0,-4.776 -3.728,-3.602 -7.918,-2.884 l -7.159,1.227 c -1.383,0.236 -5.683,1.528 -4.559,3.214 z"
id="path46" />
<path
style="fill:#417c29;stroke:#417c29;stroke-width:0.500094"
d="m 233.268,460.889 c 20.193,-0.267 68.437,-8.591 82.849,-8.965 l 23.804,-0.618 c 6.799,-0.177 16.016,-0.52 29.678,3.4 1.327,0.381 2.183,0.306 2.473,1.855 1.564,8.343 0.23,13.092 -3.401,13.911 -10.305,2.327 -10.548,11.712 -13.911,25.968 -4.472,18.958 -4.935,26.751 -6.214,30.63 -0.337,1.022 -5.611,-1.284 -17.576,2.166 -16.6,2.013 -43.935,2.959 -45.998,3.048 -42.753,1.845 -55.842,5.006 -55.842,-15.706 0,-8.795 -3.022,-55.689 4.138,-55.689 z"
id="path48" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 107.344,580.938 18.791,-35.711 c 2.997,-5.696 7.418,-11.506 14.976,-5.336 3.8,3.102 8.675,7.332 11.853,8.524 6.254,2.346 9.091,6.789 5.388,10.709 -3.077,3.256 -7.076,11.3 -9.635,17.561 -1.957,4.787 -4.355,10.724 -6.101,16.553 -5.061,16.899 -6.809,18.705 -17.285,10.333 l -4.943,-3.949 c -5.047,-4.034 -11.9,-11.919 -13.597,-13.423 -2.134,-1.891 0.981,-4.808 0.553,-5.261 z"
id="path50" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 113.135,583.573 c 2.546,3.587 7.105,8.127 10.807,10.555 3.354,2.199 5.306,4.736 9.359,5.018 0.923,0.064 1.736,-2.695 2.486,-4.534 1.091,-2.672 3.105,-11.359 3.439,-12.418 2.1,-6.664 14.43,-25.125 10.274,-28.981 -1.919,-1.781 -5.207,-3.24 -6.942,-4.976 -4.05,-4.049 -8.93,-5.791 -10.992,0.463 -1.175,3.565 -10.451,19.726 -12.959,23.488 -1.762,2.643 -5.588,8.261 -5.472,11.385 z"
id="path52" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 337.347,637.313 c -10.749,4.217 -38.481,12.749 -65.238,3.463 -10.196,11.363 1.019,10.633 12.465,9.824 10.074,-0.713 19.593,-1.061 29.914,-2.506 6.053,-0.847 14.506,0.547 20.672,0.7 4.372,0.107 3.129,-2.12 2.395,-5.504 -0.433,-1.992 -0.387,-3.984 -0.208,-5.977 z"
id="path54" />
<path
style="fill:#b6bcc6;stroke:#b6bcc6;stroke-width:0.500094"
d="m 239.955,568.996 c 2.23,8.911 -0.22,18.478 -4.334,21.548 -3.845,2.717 -2.712,3.582 -1.082,5.289 16.895,17.56 22.452,22.72 36.889,34.886 15.87,10.488 46.415,8.17 64.008,-2.299 1.45,-0.767 2.848,-2.747 2.793,-4.736 -0.633,-22.764 1.465,-55.995 8.341,-84.538 0.776,-3.397 -2.277,-3.083 -2.772,-3.108 -31.698,1.954 -55.738,4.741 -77.736,4.323 -14.084,-0.799 -37.714,3.891 -42.043,-1.983 -6.963,-10.44 -1.362,-26.19 -2.249,-38.7 -1.064,-15.025 -1.458,-36.783 3.14,-42.175 7.005,-8.217 46.451,-5.78 74.215,-11.397 31.608,-3.773 49.453,-3.142 68.912,-1.608 2.865,0.323 11.658,4.022 11.323,8.98 -0.201,4.026 -1.242,8.144 -0.23,12.729 0.804,2.953 1.61,2.361 3.534,2.608 3.334,-0.143 2.737,0.106 4.71,-0.201 2.624,-0.666 0.942,-1.432 1.291,-5.375 0.229,-14.171 -4.722,-33.729 -26.016,-54.322 -21.293,-20.592 -30.799,-20.643 -51.81,-20.334 -38.953,4.217 -60.911,15.299 -76.078,32 -20.909,27.808 -32.34,47.744 -30.032,111.02 0.163,7.889 4.383,12.397 24.472,24.345 l 10.754,13.048 z"
id="path56" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 355.62,529.278 c 0.549,-3.005 6.013,-31.122 7.105,-35.477 1.371,-5.465 1.828,-6.428 6.176,-5.192 8.566,2.438 4.819,13.435 4.049,21.132 -1.292,12.917 -2.427,24.425 -3.914,36.21 -2.907,23.042 -7.973,50.453 -13.074,74.879 -2.228,10.67 -2.534,25.814 -5.521,33.163 -0.418,1.03 -3.024,-0.418 -3.495,-2.898 -4.087,-21.524 -1.217,-34.093 -1.217,-55.593 0,-14.063 7.259,-51.817 9.891,-66.224 z"
id="path58" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 359.828,651.35 c 6.968,-42.449 16.399,-97.964 23.748,-149.613 0.306,-1.943 4.034,-6.907 5.481,-7.48 5.44,-2.914 6.286,-4.589 11.726,-7.503 25.645,1.36 54.178,4.295 79.823,5.655 16.734,5.949 29.794,11.505 40.097,19.029 4.867,2.915 6.504,12.219 2.405,17.895 -8.018,13.159 -17.424,25.551 -25.592,38.584 -19.932,31.8 -39.627,61.582 -65.259,90.194 -3.692,4.604 -11.017,13.695 -20.692,11.889 -13.677,-4.332 -28.85,-5.673 -41.673,-7.227 -7.557,-0.602 -11.054,-7.188 -10.064,-11.423 z"
id="path60" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 482.131,528.976 c -1.24,2.617 -3.135,5.104 -5.427,8.592 -1.732,2.636 -3.56,8.568 0.613,10.55 l 9.027,4.287 c 2.513,1.193 2.638,3.744 3.605,3.714 7.3,-0.23 1.515,-0.835 10.207,-7.899 1.874,-1.522 4.365,-4.669 5.873,-6.478 l 7.763,-9.313 c 8.035,-4.775 3.367,-9.623 -2.964,-12.71 -4.453,-2.172 -12.663,-5.425 -17.849,-5.425 -1.051,0 -3.537,0.906 -4.076,1.679 -2.11,3.025 -4.736,8.702 -6.772,13.003 z"
id="path62" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 392.849,500.413 75.864,3.525 c 3.249,0.151 8.808,1.341 12.127,1.974 2.804,0.536 5.621,2.533 4.794,5.218 -0.786,2.554 -11.571,16.516 -11.986,17.062 -1.95,2.567 -9.215,16.357 -14.101,16.357 -9.165,0 -20.165,-3.95 -29.753,-5.499 -9.622,-1.554 -20.341,-3.103 -30.036,-4.089 -10.1,-1.029 -12.991,-2.183 -11.844,-11.845 0.987,-8.32 -0.706,-20.87 4.935,-22.703 z"
id="path64" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 250.062,205.816 c 0.002,0 0.004,-0.001 0.006,-0.002 0.096,-0.035 0.194,-0.065 0.292,-0.091 5.797,-1.844 11.86,-4.389 18.071,-3.058 5.138,1.101 10.974,5.938 13.68,10.413 3.165,5.232 1.541,11.415 -1.495,16.3 -6.549,10.538 -20.003,18.998 -32.287,14.085 -5.353,-2.141 -10.193,-5.673 -11.845,-11.478 -1.648,-5.789 -0.555,-12.401 3.196,-17.132 l 9.062,-8.196 c 0.006,-0.007 0.014,-0.013 0.021,-0.02 0.119,-0.117 0.246,-0.226 0.382,-0.327 0.011,-0.008 0.023,-0.017 0.034,-0.025 0.019,-0.014 0.037,-0.027 0.056,-0.04 0.006,-0.004 0.011,-0.008 0.017,-0.011 0.045,-0.031 0.089,-0.061 0.135,-0.089 0.012,-0.008 0.025,-0.015 0.038,-0.023 0.197,-0.12 0.405,-0.22 0.618,-0.299 0.006,-0.002 0.012,-0.005 0.019,-0.007 z"
id="path66" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 300.245,315.651 c 1.574,0.947 2.515,-0.606 10.498,-5.352 7.187,-4.273 15.25,-7.945 20.533,-11.763 7.354,-5.315 25.549,-17.509 24.641,-25.042 -0.642,-5.321 -14.214,10.566 -18.936,14.215 -10.67,8.247 -20.691,18.004 -35.328,24.669 -1.166,0.576 -2.139,2.442 -1.408,3.273 z"
id="path68" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 238.507,279.676 c 1.909,0.597 6.445,4.889 7.159,5.369 l 6.204,4.176 c 2.387,1.552 8.966,4.859 11.693,6.205 6.46,3.188 14.731,8.157 20.762,12.409 l 9.306,6.562 c 4.417,3.114 -5.012,3.361 -11.096,-0.477 -4.609,-2.907 -13.006,-5.803 -18.733,-9.187 -4.88,-2.884 -14.437,-7.159 -18.494,-10.858 -2.563,-2.337 -5.748,-3.694 -6.682,-7.517 -0.378,-1.546 -2.148,-7.04 -0.119,-6.682 z"
id="path70" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 244.212,274.334 c 0.191,2.278 5.742,6.266 8.352,7.403 7.403,3.227 15.172,8.003 20.501,10.63 8.148,4.016 13.668,11.39 24.108,11.39 5.505,0 14.502,-7.123 18.982,-10.061 6.075,-3.983 12.067,-8.629 17.084,-13.288 l 15.945,-14.806 c 2.837,-2.634 -1.374,-4.982 -4.745,-7.593 -6.409,-4.963 -10.058,-4.947 -18.983,-10.06 -7.083,-4.059 -19.843,-7.971 -28.473,-6.644 -7.403,1.138 -18.638,6.738 -26.006,10.44 -8.674,4.358 -26.955,14.047 -26.765,22.589 z"
id="path72" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 297.904,545.735 c 2.396,-0.288 4.556,0.259 5.919,2.701 2.06,3.686 -0.232,7.974 -4.483,7.802 -3.554,-0.144 -8.933,-3.863 -6.925,-8.003 1.011,-2.084 3.189,-2.289 5.237,-2.515 0.086,0 0.169,0.005 0.252,0.015 z"
id="path74" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 294.603,560.095 c 0.438,-0.516 1.128,-0.794 1.843,-0.675 3.294,1.113 6.066,4.692 4.64,8.272 -1.198,3.005 -5.618,1.937 -7.535,0.531 -2.1,-1.54 -3.415,-4.711 -1.413,-6.86 0.701,-0.753 1.55,-1.086 2.465,-1.268 z"
id="path76" />
<path
style="fill:none;stroke:none"
d="m 295.859,248.272 -3.157,21.914 c -1.485,10.309 1.044,10.501 1.26,22.27"
id="path80" />
<path
style="fill:#1f2123;stroke:#1f2123;stroke-width:0.500094"
d="m 467.032,370.467 c -19.85,-45.516 -51.177,-74.955 -60.487,-85.241 -0.147,-0.163 -0.29,-0.322 -0.426,-0.475 -5.555,-6.336 -12.057,-13.893 -13.059,-25.558 0.993,-23.854 2.247,-42.934 0.369,-65.301 -1.801,-28.672 -6.944,-59.21 -43.6,-69.757 30.16,20.427 29.66,42.071 32.427,61.447 1.985,24.27 -1.256,56.069 -1.545,71.746 -1.87,20.407 10.016,26.761 14.744,32.878 13.685,14.682 50.186,44.053 71.577,80.261 z"
id="path82" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 464.018,508.461 c 1.79,0 13.877,1.413 10.307,7.147 -4.252,6.826 -4.648,9.844 -9.88,16.65 -7.507,9.764 -13.314,5.362 -19.591,4.304 l -23.768,-4.002 c -27.075,-4.561 -25.359,-3.802 -25.359,-8.88 l 0,-12.528 c 17.301,-3.191 36.202,1.265 53.259,-2.884 1.998,-0.461 10.603,-2.459 12.14,-0.922 0.614,0.614 2.485,0.962 2.892,1.115 z"
id="path84" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 310.591,548.58 c 0.421,-1.593 1.319,-2.973 3.257,-3.183 3.292,-0.356 9.214,2.81 8.056,6.832 -0.826,2.867 -5.66,4.193 -8.116,2.885 -1.5,-0.8 -2.313,-2.316 -3.28,-3.642 -0.776,-0.777 -0.776,-2.036 0,-2.812 0.028,-0.028 0.055,-0.054 0.083,-0.08 z"
id="path86" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 314.978,559.301 c 1.714,2.222 2.526,5.314 1.347,7.969 -1.123,2.526 -3.846,2.472 -5.775,0.918 -2.448,-1.972 -3.504,-5.559 -1.937,-8.409 0.902,-1.639 2.286,-2.359 3.948,-3.025 1.059,-0.293 2.155,0.327 2.448,1.385 0.111,0.397 0.091,0.799 -0.031,1.162 z"
id="path88" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 296.969,549.787 -0.762,0.101 -0.149,0.064 -0.024,0.014 0.015,0.074 0.118,0.279 c 0.528,0.909 4.496,3.388 4.448,1.075 -0.034,-1.639 -1.255,-2.032 -2.614,-1.707 -0.341,0.129 -0.696,0.157 -1.032,0.1 z"
id="path90" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 296.355,563.842 -1.091,0.136 -0.125,0.049 -0.014,0.007 0.005,0.026 0.082,0.191 c 0.485,0.837 1.345,1.21 2.253,1.363 l -0.064,-0.264 c -0.22,-0.528 -0.484,-1.097 -0.887,-1.516 -0.052,0.005 -0.105,0.008 -0.159,0.008 z"
id="path92" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 325.735,547.45 c 2.512,-3.106 8.664,-3.632 10.675,0.448 1.113,2.258 0.132,5.033 -2.494,5.421 -1.802,0.266 -3.656,-0.584 -5.293,-1.182 l -0.453,-0.175 -0.077,-0.028 c -1.058,-0.045 -1.901,-0.916 -1.901,-1.986 0,-0.004 10e-4,-0.007 10e-4,-0.01 -0.715,-0.6 -0.929,-1.641 -0.458,-2.488 z"
id="path94" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 330.829,558.627 c 2.469,1.107 6.172,2.711 5.033,5.892 -1.471,4.106 -8.986,4.958 -10.499,0.49 -0.97,-2.866 0.848,-5.174 3.004,-6.765 0.824,-0.475 1.847,-0.293 2.462,0.383 z"
id="path96" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 270.164,546.402 c 4.619,-1.875 11.107,-0.078 13.616,4.334 3.166,5.567 4.467,12.057 -1.42,16.231 -5.239,3.714 -14.483,3.822 -18.817,-1.429 -4.008,-4.856 -3.843,-12.723 1.146,-16.827 1.685,-1.386 3.495,-1.985 5.475,-2.309 z"
id="path98" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 267.302,556.065 c -0.123,0.483 -0.16,1.019 -0.089,1.608 0.684,5.661 7.078,6.884 11.448,3.938 3.969,-2.675 -0.421,-9.713 -4.77,-9.419 -0.035,0.021 -0.07,0.042 -0.106,0.061 1.06,0.754 1.606,2.106 1.271,3.444 -0.436,1.744 -2.202,2.804 -3.946,2.368 -1.231,-0.445 -2.677,-1.094 -3.808,-2 z"
id="path100" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 314.265,550.164 c 0.558,0.884 1.21,1.628 2.302,1.336 l 1.17,-0.385 -0.125,-0.195 -0.777,-0.741 -0.912,-0.556 c -1.298,-0.666 -1.573,-0.493 -1.658,0.541 z"
id="path102" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 312.107,561.91 c -0.448,0.921 -0.245,2.067 0.686,2.959 l 0.006,-0.231 c -0.09,-0.906 -0.214,-1.927 -0.692,-2.728 z"
id="path104" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 331.605,548.968 c 0.264,0.096 0.51,0.183 0.73,0.246 l 0.268,0.06 c -0.226,-0.183 -0.588,-0.276 -0.998,-0.306 z"
id="path106" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 329.538,562.469 c -0.456,0.535 -0.812,1.194 -0.249,1.513 0.617,0.35 1.63,-0.199 2.201,-0.501 l -1.952,-1.012 z"
id="path108" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 253.347,563.463 c -0.005,0.891 -0.374,1.778 -1.093,2.417 -4.581,3.154 -9.342,5.848 -15.118,4.294 -8.297,-2.233 -12.905,-12.736 -8.108,-20.108 4.297,-6.603 12.28,-5.68 18.964,-4.055 6.926,1.685 6.809,9.464 6.065,15.006 -0.111,0.827 -0.347,1.671 -0.71,2.446 z"
id="path110" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 245.615,557.205 1.955,1.829 0.173,0.129 c 0.369,-2.508 1.144,-6.356 -2.013,-7.049 -4.155,-0.912 -10.961,-2.255 -12.048,3.552 -0.648,3.462 1.699,7.306 5.124,8.218 1.523,0.405 2.936,0.267 4.272,-0.171 -0.713,-0.645 -1.394,-1.312 -2.065,-1.906 -1.271,-1.271 -1.271,-3.331 0,-4.602 1.271,-1.27 3.331,-1.27 4.602,0 z"
id="path112" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 248.165,498.513 9.59,-5.826 c 5.089,-2.321 10.436,-1.122 15.858,-1.833 5.609,-0.735 12.658,-3.012 13.985,-9.454 0.905,-4.396 1.957,-10.386 -0.558,-14.532 -4.122,-6.792 -14.222,-5.811 -20.805,-5.094 -8.498,0.925 -17.133,4.004 -23.302,10.112 -4.848,4.802 -6.515,10.098 -8.147,16.164 -1.436,4.793 -0.679,10.423 4.714,12.833 3.608,1.613 6.177,-0.82 8.665,-2.37 z"
id="path114" />
<path
style="fill:#adeca8;stroke:#adeca8;stroke-width:0.500094"
d="m 243.091,493.939 c -2.522,1.479 -1.809,-3.165 -1.428,-4.431 1.467,-5.428 2.725,-9.551 6.491,-13.262 7.051,-6.946 17.425,-8.622 26.914,-8.729 1.566,-0.018 6.883,0.236 7.2,2.857 0.376,3.109 1.222,9.121 -1.906,11.536 -4.483,3.463 -11.499,2.193 -16.693,2.52 -6.009,0.377 -16.307,5.274 -20.578,9.509 z"
id="path116" />
<path
style="fill:#d2f799;stroke:#d2f799;stroke-width:0.500094"
d="m 354.161,499.012 c -0.272,1.187 -0.527,2.326 -0.768,3.421 -0.338,0.189 -0.727,0.297 -1.143,0.297 -4.945,0.382 -11.024,2.019 -16,0.841 -4.57,-1.082 -11.365,-1.696 -15.436,1.133 -2.722,1.891 -5.949,2.138 -7.052,-1.628 l -0.302,-1.363 -0.251,-0.916 -0.048,-0.099 -0.203,-0.012 -0.281,0.021 c -3.75,0.506 -4.53,8.779 -9.192,7.069 -1.632,-0.599 -2.74,-2.446 -3.184,-4.04 l -2.815,-13.974 -2.945,7.099 -5.55,13.378 -0.123,0.27 c -0.657,1.512 -2.907,2.17 -4.084,0.831 -2.1,-2.391 -1.432,-6.373 -3.136,-9.1 -0.732,-1.172 -1.882,-0.377 -2.554,0.552 -2.409,3.338 -2.384,10.958 -8.461,9.154 -3.411,-1.013 -5.846,-4.166 -8.86,-5.908 -1.083,-0.626 -2.643,0.76 -3.517,1.042 -1.625,0.524 -3.309,0.828 -5.013,0.927 l -24.278,1.003 c -0.013,0.001 -0.025,0.001 -0.038,0.001 -0.048,-1.448 -0.101,-3.025 -0.153,-4.697 l 24.469,-1.007 c 3.394,-0.178 6.875,-3.345 10.27,-1.635 3.025,1.522 5.209,4.17 8.199,5.667 l 0.3,0.114 0.073,0.017 0.066,-0.092 0.271,-0.546 0.649,-1.846 c 1.467,-4.016 4.782,-10.124 10.106,-7.549 2.026,0.98 3.155,3.19 3.842,5.287 l 3.18,-7.664 5.549,-13.374 0.195,-0.393 c 0.834,-1.772 3.416,-1.502 4.306,0.008 0.84,1.425 1.067,3.552 1.349,5.074 l 1.847,10.588 1.244,5.087 0.044,0.1 c 2.301,-3.184 5.273,-7.203 9.794,-5.979 1.446,0.391 2.517,1.517 3.053,2.898 l 0.474,1.651 0.034,0.156 c 2.411,-1.603 4.47,-2.192 7.402,-2.454 l 2.697,-0.205 5.26,-0.01 4.167,0.903 -0.189,-0.091 0.262,0.043 0.549,0.036 0.749,0.003 13.265,-1.071 c 0.788,0 1.485,0.386 1.911,0.982 z"
id="path118" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 278.606,344.29 c -1.223,1.27 -1.84,2.793 -0.933,5.004 0.926,2.258 2.897,2.929 5.159,2.419 1.802,-0.407 1.022,-3.574 0.275,-4.557 -1.003,-1.318 -2.834,-2.127 -4.501,-2.866 z"
id="path120" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 275.57,323.019 c -1.01,1.039 -2.043,2.361 -1.315,3.471 0.678,1.033 1.636,1.807 2.78,2.284 l 0.666,0.221 0.525,0.075 0.154,-0.03 -0.015,0.009 -0.166,0.107 -0.186,0.165 0.129,-0.02 0.264,-0.266 0.073,-0.014 -0.015,-0.033 -0.039,0.024 0.297,-0.475 c 1.486,-2.902 -0.87,-4.241 -3.152,-5.518 z"
id="path122" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 279.961,366.995 c -0.52,1.717 -0.801,3.474 -0.377,5.381 l 0.215,0.479 0.098,0.115 0.068,0.028 0.018,-0.048 -0.044,-0.096 -0.093,-0.107 c -0.575,-0.601 2.303,-0.597 2.453,-1.441 0.268,-1.507 -0.934,-3.019 -2.338,-4.311 z"
id="path124" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 388.055,491.931 c 7.415,11.614 8.662,20.574 14.84,31.834 10.514,16.263 28.007,11.836 31.437,10.404 11.73,-5.163 20.5,-17.082 36.88,-28.388 7.006,-6.081 10.829,-15.698 8.995,-19.834 l -83.308,0.82 -8.844,5.164 z"
id="path126" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 413.013,523.761 c -1.306,-0.979 -5.262,-8.427 -6.448,-11.599 -2.689,-7.194 -9.113,-16.83 -9.113,-24.883 0,-8.272 -3.863,-12.212 7.597,-16.81 12.486,-5.009 26.287,-6.181 40.838,-4.396 8.287,1.016 20.914,4.329 25.404,10.903 3.275,4.795 -1.478,18.075 -4.536,20.911 l -17.767,16.482 c -3.862,3.582 -12.447,11.546 -19.63,11.546 -2.612,0 -10.924,1.2 -16.345,-2.154 z"
id="path128" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 497.371,520.641 c -4.763,0.772 -11.951,14.588 -14.838,19.526 -3.306,5.657 8.621,8.418 10.232,7.836 4.678,-1.689 7.925,-7.893 8.963,-9.035 2.214,-2.431 10.48,-11.767 7.515,-13.185 -5.084,-2.431 -6.622,-4.793 -11.872,-5.142 z"
id="path130" />
<path
style="fill:none;stroke:none"
d="m 253.108,272.087 c 5.49,-0.845 -0.845,5.912 -0.845,0.422"
id="path134" />
<path
style="fill:none;stroke:none"
d="m 264.51,280.111 c 1.267,-1.056 3.59,-2.956 3.167,0.211 -0.422,2.956 -4.223,-0.634 -2.322,-1.478"
id="path138" />
<path
style="fill:none;stroke:none"
d="m 276.757,287.923 c 0,-8.235 1.056,4.857 0,0.423 -0.422,-1.689 -4.434,1.056 -0.845,-3.168"
id="path142" />
<path
style="fill:none;stroke:none"
d="m 302.307,291.302 c -0.845,-2.745 3.8,-1.689 5.067,-0.422 1.69,1.689 -1.478,4.012 -3.378,1.478"
id="path146" />
<path
style="fill:none;stroke:none"
d="m 318.777,282.645 c 0,-1.69 2.534,-4.012 4.223,-2.534 1.478,1.267 -3.167,3.589 -3.167,1.689"
id="path150" />
<path
style="fill:none;stroke:none"
d="m 338.414,269.342 c -7.39,-2.323 6.546,0.844 -0.211,0.844"
id="path154" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 258.581,132.113 0.295,-1.44 0.068,-0.213 c 0.13,-1.175 1.126,-2.09 2.335,-2.09 1.298,0 2.351,1.053 2.351,2.351 l -0.295,1.44 -0.067,0.209 c -0.128,1.178 -1.126,2.094 -2.337,2.094 -1.298,0 -2.35,-1.053 -2.35,-2.351 z"
id="path156" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 248.739,141.528 c -1.601,-1.055 -3.019,-2.672 -1.344,-4.398 0.638,-0.657 1.543,-0.682 2.394,-0.751 1.298,0 2.35,1.052 2.35,2.35 0,0.118 -0.008,0.235 -0.025,0.348 0.07,0.462 0.002,0.949 -0.222,1.398 -0.58,1.162 -1.992,1.633 -3.153,1.053 z"
id="path158" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 273.344,131.02 c -1.546,-0.923 -4.112,-2.434 -2.777,-4.654 0.924,-1.537 2.721,-1.426 4.292,-1.478 1.298,0 2.35,1.053 2.35,2.351 0,0.479 -0.143,0.926 -0.39,1.297 0.103,0.533 0.022,1.102 -0.268,1.61 -0.644,1.127 -2.08,1.518 -3.207,0.874 z"
id="path160" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 284.175,129.549 c -2.051,-0.676 -4.142,-1.562 -3.837,-4.14 0.318,-2.692 4.103,-4.802 6.369,-3.022 1.622,1.274 0.924,3.253 0.351,4.858 -0.033,0.067 -0.069,0.132 -0.107,0.194 -0.007,0.077 -0.018,0.154 -0.033,0.232 -0.239,1.276 -1.467,2.117 -2.743,1.878 z"
id="path162" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 295.985,129.891 c -2.559,-0.803 -5.481,-2.802 -3.529,-5.832 2.278,-3.537 6.42,-1.396 6.688,2.135 0,0.455 -0.129,0.88 -0.353,1.24 0.013,0.201 10e-4,0.407 -0.04,0.614 -0.255,1.273 -1.493,2.098 -2.766,1.843 z"
id="path164" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 304.59,127.023 c -1.264,-1.217 -2.255,-2.819 -0.603,-4.278 2.369,-2.09 7.775,0.524 7.487,3.692 -0.203,2.232 -2.984,2.327 -4.582,2.455 -1.134,0 -2.08,-0.801 -2.302,-1.869 z"
id="path166" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 323.257,130.982 c -2.279,-0.159 -6.378,-1.101 -4.858,-4.386 0.991,-2.14 4.238,-2.946 6.174,-1.692 1.238,0.802 1.592,1.996 1.73,3.379 0,1.059 -0.701,1.956 -1.664,2.249 -0.388,0.283 -0.865,0.45 -1.382,0.45 z"
id="path168" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 347.404,135.83 c 1.612,-0.767 3.365,-1.131 4.585,0.341 2.392,2.885 -2.249,7.396 -5.332,6.304 -0.484,-0.172 -0.87,-0.424 -1.178,-0.735 -0.61,-0.108 -1.176,-0.456 -1.546,-1.011 -0.639,-0.96 -0.481,-2.217 0.32,-2.991 0.145,-1.159 1.134,-2.056 2.332,-2.056 0.288,0 0.563,0.053 0.819,0.148 z"
id="path170" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 333.793,128.576 c 0.106,-0.45 0.326,-0.886 0.643,-1.264 0.917,-0.917 2.405,-0.917 3.323,0 0.114,0.114 0.213,0.237 0.298,0.366 l 0.526,0.32 c 5.453,4.065 -5.784,10.141 -7.365,4.423 -0.584,-2.109 0.855,-3.252 2.575,-3.845 z"
id="path172" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 354.483,150.534 c -1.804,-0.746 -3.844,-2.061 -2.933,-4.384 1.936,-4.935 11.861,-1.797 9.861,3.125 -1.051,2.586 -4.114,2.004 -6.278,1.367 -0.216,-0.005 -0.433,-0.04 -0.65,-0.108 z"
id="path174" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 360.204,158.846 c -0.105,-2.008 0.136,-4.362 2.498,-4.857 3.39,-0.711 8.413,5.566 5.38,8.381 -2.079,1.931 -5.001,-0.248 -6.843,-1.316 -0.755,-0.503 -1.125,-1.365 -1.035,-2.208 z"
id="path176" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.681,173.358 c -1.285,-1.236 -3.668,-3.339 -2.048,-5.343 2.096,-2.594 8.802,-1.036 8.998,2.547 0.132,2.399 -2.365,2.849 -4.335,3.002 -0.808,0.455 -1.843,0.405 -2.615,-0.206 z"
id="path178" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.97,179.521 c 0.668,-1.088 1.676,-1.799 3.206,-1.515 3.973,0.735 4.505,7.545 0.586,8.807 -1.584,0.509 -2.862,0.193 -3.827,-0.585 -0.49,-0.268 -0.875,-0.705 -1.074,-1.234 -0.569,-0.907 -0.927,-2.018 -1.07,-3.13 0,-1.24 0.961,-2.256 2.179,-2.343 z"
id="path180" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.882,195.121 c 10e-4,-0.008 0.003,-0.016 0.004,-0.024 -0.889,-1.11 -1.154,-2.552 -1.171,-3.948 0.08,-1.296 1.194,-2.282 2.49,-2.202 0.692,0.042 1.294,0.381 1.695,0.883 0.619,-0.226 1.356,-0.221 2.233,0.125 2.109,0.832 3.322,3.976 1.812,5.832 -0.724,0.89 -1.832,1.239 -2.977,1.206 -0.502,0.564 -1.264,0.875 -2.067,0.768 -1.287,-0.171 -2.191,-1.353 -2.019,-2.64 z"
id="path182" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.711,243.253 c -2.14,-1.948 -2.704,-4.666 10e-4,-6.518 3.673,-2.514 8.917,1.307 7.159,5.589 -0.739,1.801 -2.816,2.734 -4.647,2.049 -0.488,-0.183 -0.883,-0.437 -1.205,-0.746 -0.448,0.007 -0.902,-0.113 -1.308,-0.374 z"
id="path184" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 363.062,253.311 c 0.952,-2.018 2.271,-4.97 5.094,-3.857 3.461,1.365 4.881,8.753 1.239,10.632 -2.308,1.191 -4.24,-0.67 -5.954,-2.015 -0.824,-0.823 -0.909,-2.105 -0.255,-3.022 -0.254,-0.523 -0.314,-1.141 -0.124,-1.738 z"
id="path186" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 364.477,277.674 c -0.51,-1.449 -0.608,-2.979 1.097,-3.86 2.79,-1.442 7.426,1.83 6.267,4.997 -0.809,2.211 -3.385,2.253 -5.347,2.42 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.442 0.121,-0.854 0.333,-1.207 z"
id="path188" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 368.32,291.409 c 0.229,-2.722 1.853,-4.523 4.755,-4.29 2.14,0.172 5.586,1.881 5.324,4.485 -0.082,0.812 -0.473,1.503 -1.105,1.974 -0.897,2.04 -3.853,3.126 -5.815,1.565 -0.436,-0.346 -0.755,-0.844 -0.913,-1.386 -1.25,-0.055 -2.246,-1.085 -2.246,-2.348 z"
id="path190" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 377.875,299.502 c 1.985,-2.181 5.125,-4.315 8.258,-3.062 4.838,1.933 2.627,6.95 -1.028,8.511 -1.377,0.588 -3.667,0.859 -4.576,-0.729 l -0.482,-0.954 -0.009,-0.031 c -0.135,-0.074 -0.263,-0.16 -0.38,-0.258 -0.297,-0.035 -0.592,-0.127 -0.869,-0.281 -1.135,-0.63 -1.544,-2.061 -0.914,-3.196 z"
id="path192" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 392.26,312.253 c -0.088,-0.028 -0.176,-0.057 -0.265,-0.088 -0.489,-0.021 -0.978,-0.067 -1.465,-0.124 -1.004,-0.287 -1.669,-1.185 -1.704,-2.175 -0.354,-0.697 -0.408,-1.54 0.029,-2.546 1.312,-3.02 5.725,-3.056 7.872,-1.031 1.485,1.401 1.599,3.812 -0.297,4.949 -0.871,0.523 -1.805,0.784 -2.763,0.887 -0.43,0.181 -0.917,0.235 -1.407,0.128 z"
id="path194" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 416.208,335.904 c -1.787,-1.168 -5.454,-3.337 -3.163,-5.92 1.933,-2.177 6.675,-0.549 8.742,0.445 1.594,0.766 3.03,2.821 1.53,4.446 -1.343,1.456 -3.449,1.223 -5.255,1.33 -0.12,0 -0.237,-0.008 -0.352,-0.025 -0.5,0.076 -1.027,-0.009 -1.502,-0.276 z"
id="path196" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 399.133,321.246 c 0.205,-2.1 1.113,-4.444 3.573,-4.702 2.95,-0.308 7.779,2.181 5.944,5.797 -1.292,2.546 -4.799,2.423 -7.167,2.585 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.231 0.033,-0.453 0.095,-0.664 -0.062,-0.211 -0.095,-0.435 -0.095,-0.666 z"
id="path198" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 426.369,342.627 c 1.879,-3.041 6.734,-5.137 8.725,-0.834 1.964,4.248 -2.58,8.094 -6.659,6.823 -1.794,-0.559 -2.773,-1.822 -3.223,-3.558 -0.167,-1 0.324,-1.958 1.157,-2.431 z"
id="path200" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 438.823,359.598 c -2.112,-2.05 -2.069,-5.044 0.695,-6.536 2.849,-1.537 10.774,-2.028 9.626,3.426 -0.612,2.904 -4.519,5.618 -7.434,4.246 -0.372,-0.174 -0.685,-0.389 -0.947,-0.633 -0.665,0.125 -1.379,-0.036 -1.94,-0.503 z"
id="path202" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 449.504,367.991 c 0.459,-0.329 1.067,-0.468 1.873,-0.309 0.257,0.051 0.493,0.131 0.711,0.237 0.937,0.219 1.782,0.744 2.377,1.668 1.118,1.733 0.507,3.586 0.005,5.409 -0.472,1.209 -1.835,1.807 -3.044,1.335 -0.049,-0.019 -0.097,-0.04 -0.143,-0.062 -0.622,0.139 -1.337,0.049 -2.137,-0.361 -2.418,-1.242 -5.124,-4.361 -2.165,-6.683 0.713,-0.56 1.597,-0.997 2.523,-1.234 z"
id="path204" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 460.887,383.928 c 3.505,0.279 5.866,5.971 1.895,7.43 -0.798,0.293 -1.833,0.308 -2.896,0.097 -0.212,0.063 -0.435,0.097 -0.668,0.097 -0.841,0 -1.58,-0.443 -1.995,-1.108 -1.795,-1.054 -3.056,-2.75 -2.397,-4.745 0.655,-1.985 2.585,-2.299 4.392,-2.467 0.653,0 1.243,0.266 1.669,0.696 z"
id="path206" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 467.474,406.964 c -1.798,-0.783 -4.577,-1.752 -4.449,-4.19 0.243,-4.596 7.857,-3.291 9.328,-0.216 0.799,1.672 -0.362,3.365 -1.397,4.581 -0.917,0.918 -2.406,0.918 -3.323,0 -0.056,-0.056 -0.11,-0.115 -0.159,-0.175 z"
id="path208" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 471.216,427.057 c -0.902,0.345 -1.961,0.109 -2.624,-0.667 -1.052,-1.672 -2.519,-4.08 -0.899,-5.961 3.011,-3.497 11.708,-1.604 9.869,3.93 -0.874,2.629 -3.395,3.192 -5.823,2.897 -0.185,-0.046 -0.361,-0.114 -0.523,-0.199 z"
id="path210" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 475.942,438.485 c 1.04,0.598 1.771,1.552 1.635,3.044 -0.365,3.995 -4.595,6.317 -8.19,4.632 -2.125,-0.996 -2.207,-3.938 -1.071,-5.677 1.332,-2.04 2.826,-3.25 5.14,-3.829 1.185,-0.098 2.236,0.701 2.486,1.83 z"
id="path212" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 471.258,456.124 c 0.386,-0.77 1.183,-1.299 2.104,-1.299 0.102,0.012 0.202,0.024 0.303,0.04 0.752,-0.142 1.498,0.094 2.029,0.584 1.757,0.801 2.979,2.317 2.715,4.613 -0.475,4.132 -7.629,3.931 -8.864,0.393 -0.687,-1.966 0.309,-3.341 1.713,-4.331 z"
id="path214" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.05,136.106 -0.139,0.028 c -1.915,0.308 -2.917,-4.254 -0.852,-4.624 l 0.028,-0.004 0.013,-0.002 0.237,-0.046 0.543,-0.107 c 0.244,-0.049 0.487,-0.057 0.721,-0.031 l 0.122,-0.014 c 1.298,0 2.35,1.052 2.35,2.35 0,1.298 -1.052,2.35 -2.35,2.35 l -0.243,0.031 -0.43,0.069 z m -0.934,-4.603 0.138,-0.017 -0.077,0.007 -0.061,0.01 z"
id="path216" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 369.676,143.446 c -0.73,-1.424 -1.183,-3.038 0.349,-4.226 2.433,-1.888 7.486,0.678 7.014,3.865 -0.369,2.494 -3.007,2.667 -5.016,2.848 -1.298,0 -2.351,-1.052 -2.351,-2.35 0,-0.046 0.002,-0.091 0.004,-0.137 z"
id="path218" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 377.559,149.633 c 2.461,0.216 5.758,1.845 3.748,4.84 -2.11,3.146 -5.866,0.999 -6.098,-2.108 0,-0.065 0.002,-0.128 0.007,-0.191 -0.005,-0.062 -0.007,-0.127 -0.007,-0.191 0,-1.298 1.052,-2.35 2.35,-2.35 z"
id="path220" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 379.959,162.946 c 1.656,-2.842 7.349,-4.245 7.766,0.257 0.217,2.345 -1.576,3.53 -3.67,3.906 l -0.78,0.056 -0.127,0.004 c -0.834,0.31 -1.808,0.128 -2.478,-0.543 -0.444,-0.587 -0.645,-1.201 -0.64,-1.772 -0.282,-0.576 -0.328,-1.266 -0.071,-1.908 z"
id="path222" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 383.505,173.306 c 0.408,-0.464 0.965,-0.796 1.716,-0.895 2.871,-0.379 5.553,2.274 4.671,5.22 -0.998,3.337 -5.939,2.471 -7.795,0.519 -0.68,-0.716 -0.877,-1.557 -0.97,-2.495 0,-1.298 1.052,-2.35 2.35,-2.35 0.01,0 0.018,0.001 0.028,0.001 z"
id="path224" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 382.848,189.533 c -0.692,-2.067 -0.586,-4.342 1.826,-5.219 2.908,-1.057 6.147,1.237 6.537,4.197 0.597,4.515 -5.16,4.508 -7.677,2.551 -0.426,-0.425 -0.655,-0.972 -0.686,-1.529 z"
id="path226" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 385.826,251.827 c 0.448,-0.282 0.994,-0.415 1.56,-0.34 2.588,0.689 4.562,2.821 3.173,5.606 -1.853,3.717 -9.312,3.173 -9.144,-1.467 0.081,-2.231 2.086,-3.249 3.969,-3.759 0.149,-0.028 0.296,-0.04 0.442,-0.04 z"
id="path228" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 386.265,263.315 c 0.335,-0.124 0.705,-0.173 1.085,-0.128 2.768,0.504 5.201,2.744 2.977,5.488 -1.55,1.913 -5.537,3.367 -7.431,1.148 -1.53,-1.793 -0.309,-3.859 0.604,-5.606 0.615,-0.922 1.768,-1.269 2.765,-0.902 z"
id="path230" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 397.797,276.344 c 0.283,0.115 0.55,0.287 0.779,0.517 1.776,2.071 2.07,4.986 -0.942,6.03 -2.414,0.836 -6.668,-0.274 -6.38,-3.45 0.19,-2.092 2.279,-2.926 3.902,-3.74 0.953,-0.378 2.005,-0.089 2.641,0.643 z"
id="path232" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 406.747,287.629 c 1.08,1.17 2.031,2.637 0.739,4.121 -1.914,2.197 -6.854,0.34 -7.576,-2.23 -0.801,-2.85 2.146,-3.659 4.282,-4.053 1.292,-0.117 2.435,0.836 2.552,2.129 10e-4,0.011 0.002,0.022 0.003,0.033 z"
id="path234" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 412.436,296.028 c 0.519,-0.573 1.31,-0.88 2.129,-0.744 0.249,0.042 0.48,0.121 0.693,0.231 1.15,0.091 2.087,1.018 2.157,2.203 0.073,1.233 -0.819,2.301 -2.022,2.467 -0.938,1.183 -2.313,1.838 -3.894,0.742 -1.431,-0.991 -1.405,-3.103 -0.147,-4.23 0.334,-0.299 0.698,-0.511 1.084,-0.669 z"
id="path236" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 424.19,304.681 c 0.203,0.103 0.399,0.224 0.582,0.359 0.918,0.917 0.918,2.406 0,3.323 -0.127,0.128 -0.266,0.239 -0.413,0.33 l -0.242,0.261 c -2.285,2.125 -7.717,-1.007 -5.61,-4.009 0.935,-1.333 2.532,-1.156 3.947,-1.031 0.688,0 1.306,0.296 1.736,0.767 z"
id="path238" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 425.898,314.312 c 0.185,-0.588 0.599,-1.104 1.194,-1.401 0.692,-0.345 1.472,-0.317 2.113,0.008 1.012,0.178 1.825,1.009 1.931,2.082 0.084,0.84 -0.287,1.622 -0.913,2.101 -0.393,0.75 -1.151,1.242 -2.365,1.144 -1.934,-0.158 -2.884,-2.345 -1.96,-3.934 z"
id="path240" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 435.675,320.542 c 0.082,-0.038 0.168,-0.072 0.255,-0.102 1.232,-0.41 2.562,0.256 2.972,1.488 0.528,2.539 -0.813,5.337 -3.869,4.182 -2.886,-1.091 -2.514,-4.572 0.198,-5.502 0.149,-0.037 0.297,-0.058 0.444,-0.066 z"
id="path242" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 445.007,334.777 -0.167,0.037 c -0.586,0.573 -1.399,0.778 -2.147,0.614 -1.271,0.116 -2.358,-0.497 -2.781,-1.725 -0.563,-1.638 1.098,-2.364 2.597,-2.923 l -0.176,-0.027 -0.231,0.013 -0.037,0.004 0.215,-0.061 0.377,-0.097 0.336,-0.011 c 0.375,-0.139 0.721,-0.272 0.995,-0.412 1.267,-0.282 2.522,0.517 2.804,1.784 0.281,1.267 -0.518,2.522 -1.785,2.804 z"
id="path244" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 450.342,340.548 c 1.425,-0.225 3.788,0.036 3.482,2.21 -0.224,1.591 -1.118,2.111 -2.484,2.468 -1.231,0.41 -2.562,-0.256 -2.972,-1.488 -0.302,-0.906 -0.021,-1.868 0.64,-2.475 0.341,-0.366 0.802,-0.626 1.334,-0.715 z"
id="path246" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 460.356,355.597 -0.009,0.25 c 0,1.298 -1.052,2.35 -2.35,2.35 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.002 0,-0.003 0,-0.005 -0.085,-0.243 -0.13,-0.502 -0.13,-0.774 0,-0.511 0.162,-0.984 0.438,-1.369 0.364,-1.387 1.147,-2.565 2.921,-2.084 2.102,0.571 2.299,2.497 1.48,3.982 z"
id="path248" />
<path
style="fill:#363a40;stroke:#363a40;stroke-width:0.500094"
d="m 253.064,212.441 c -5.171,4.318 -10.465,7.777 -10.015,15.252 0.375,6.204 7.982,11.066 13.918,10.177 7.031,-1.054 13.803,-6.459 17.537,-12.357 1.513,-2.39 3.1,-5.964 1.417,-8.698 -1.686,-2.738 -5.801,-6.44 -9.071,-7.093 -4.592,-0.918 -9.509,1.309 -13.786,2.719 z"
id="path250" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 257.655,218.342 c 0.316,-0.529 0.892,-0.885 1.553,-0.885 4.255,-0.088 8.971,-0.311 9.321,4.987 0.35,5.292 -4.997,8.682 -9.95,7.972 -3.979,-0.57 -6.853,-4.746 -5.027,-8.579 0.897,-1.881 2.39,-2.854 4.103,-3.495 z"
id="path252" />
<path
style="fill:#676f79;stroke:#676f79;stroke-width:0.500094"
d="m 261.148,221.058 c -1.818,0.434 -5.856,1.65 -4.226,4.412 1.493,2.531 5.837,1.327 7.435,-0.466 0.595,-0.668 1.069,-2.976 0.261,-3.602 -0.684,-0.529 -1.77,-0.596 -2.852,-0.539 -0.187,0.099 -0.395,0.167 -0.618,0.195 z"
id="path254" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 339.682,197.571 c 1.215,0.322 2.419,0.677 3.6,1.078 l 0.447,0.078 c 0.22,0.081 0.427,0.183 0.62,0.299 5.77,2.13 10.813,5.503 13.201,11.816 3.645,9.638 -1.143,20.015 -10.924,23.128 -9.795,3.118 -21.6,-0.139 -29.443,-6.387 -7.77,-6.189 -6.575,-17.605 1.339,-23.199 5.546,-3.921 11.631,-6.957 18.577,-6.822 l 0.935,0.165 c 0.514,-0.173 1.075,-0.235 1.648,-0.156 z"
id="path256" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 367.648,208.65 c -0.828,-1.835 -1.187,-4.404 1.262,-5.25 3.401,-1.173 8.014,1.285 8.553,4.948 0.465,3.162 -3.471,4.728 -5.774,2.88 l -0.593,-0.542 -0.14,-0.154 c -0.578,-0.05 -1.127,-0.313 -1.528,-0.75 -0.713,-0.072 -1.383,-0.47 -1.78,-1.132 z"
id="path258" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 390.23,199.555 c 1.369,0.808 2.247,2.179 1.193,3.934 -1.386,2.308 -4.828,3.856 -6.935,1.592 -2.861,-3.076 0.102,-6.767 3.509,-7.144 1.042,0 1.925,0.679 2.233,1.618 z"
id="path260" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 389.354,226.668 c 0.194,0.04 0.387,0.105 0.573,0.198 1.94,1.137 3.546,3.258 1.817,5.377 -1.657,2.033 -5.761,2.287 -7.14,-0.19 -1.091,-1.96 0.14,-3.683 1.202,-5.303 0.828,-1 2.309,-1.14 3.309,-0.312 0.086,0.072 0.165,0.149 0.239,0.23 z"
id="path262" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 387.935,238.324 c 1.766,0.591 2.974,2.125 2.714,4.332 -0.485,4.124 -6.678,2.461 -7.65,-0.568 -0.778,-2.424 0.721,-4.151 2.891,-4.897 0.88,-0.176 1.738,0.32 2.045,1.133 z"
id="path264" />
<path
style="fill:#363a40;stroke:#363a40;stroke-width:0.500094"
d="m 341.837,205.679 c -0.206,-0.037 -0.411,-0.093 -0.613,-0.168 -8.084,-1.745 -19.919,1.53 -22.156,10.598 -0.913,3.702 3.72,7.021 6.318,8.344 5.656,2.881 12.88,4.524 19.114,2.605 6.725,-2.07 9.018,-9.937 5.181,-15.739 -1.977,-2.989 -4.74,-4.555 -7.844,-5.64 z"
id="path266" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.999,225.171 c -0.748,-0.677 -1.119,-1.572 -0.487,-2.786 1.09,-2.093 4.368,-1.388 6.141,-1.099 1.565,0.255 3.25,1.189 2.963,3.028 -0.34,2.178 -3.015,2.23 -5.019,2.25 -0.292,0.063 -0.6,0.072 -0.907,0.016 -0.189,0.008 -0.364,0.018 -0.521,0.035 -0.977,0 -1.816,-0.595 -2.17,-1.444 z"
id="path268" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 385.323,213.679 c 0.285,-0.221 0.619,-0.373 0.974,-0.444 0.344,-0.127 0.702,-0.23 1.064,-0.312 1.161,-0.11 2.203,0.643 2.493,1.734 1.519,1.098 2.718,2.616 1.919,4.525 -1.616,3.856 -8.376,2.319 -8.613,-1.73 -0.107,-1.816 0.829,-3.026 2.163,-3.773 z"
id="path270" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 335.279,211.744 c 0.345,-0.328 0.818,-0.52 1.331,-0.496 0.344,0.029 0.689,0.064 1.037,0.104 0.809,-0.098 1.623,-0.169 2.427,-0.233 0.776,0 1.437,0.49 1.694,1.177 1.986,0.819 3.491,2.272 3.72,4.956 0.668,7.847 -9.275,8.891 -14.504,5.611 -2.58,-1.618 -3.987,-5 -1.947,-7.541 1.66,-2.067 3.868,-3.051 6.242,-3.578 z"
id="path272" />
<path
style="fill:#676f79;stroke:#676f79;stroke-width:0.500094"
d="m 337.752,214.937 c -2.207,0.259 -4.337,0.822 -5.907,2.663 -0.566,0.664 0.195,1.399 0.705,1.857 2.565,2.304 11.124,2.53 9.15,-2.767 -0.524,-1.406 -2.405,-1.657 -3.948,-1.753 z"
id="path274" />
</g>
<g
id="g276" />
</svg>
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doc/gw-test-procedure/gw-test-procedure.bib 0 → 100644
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@misc{conv-ttl-rs485-ohwr,
title = {{CONV-TTLRS485 Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{ctb-repo,
title = {{Conv TTL Blocking Repository on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/repository}}
}
doc/gw-test-procedure/gw-test-procedure.tex 0 → 100644
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%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
\usepackage{amssymb}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\thispagestyle{empty}
\addcontentsline{toc}{section}{Licensing information}
\section*{Licensing information}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see \\
\url{http://creativecommons.org/licenses/by-sa/4.0/}
\section*{Revision history}
\addcontentsline{toc}{section}{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
16-12-2014 & 0.1 & First draft \\
\hline
\end{tabular}
}
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents the test procedure to be performed prior to the release of
every gateware version of the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} board.
The purpose is to test all the basic features of the board prior to releasing
a new gateware version. The following features are tested:
\begin{itemize}
\item basic pulse conversion and repetition on all channels
\begin{itemize}
\item TTL to TTL
\item TTL to RS-485
\item RS-485 to TTL
\item TTL-BAR to TTL-BAR
\item TTL-BAR to RS-485
\item RS-485 to TTL-BAR
\item RS-485 to RS-485
\item TTL to TTL-BAR (basic pulse inversion)
\end{itemize}
\item no pulses generated on power-on
\end{itemize}
%==============================================================================
% SEC: Test preparation
%==============================================================================
\pagebreak
\section{Test preparation}
\label{sec:prep}
This section lists the steps to be taken prior to starting the actual test.
It is recommended to follow the steps listed in the following subsections \textbf{in
sequence}.
%==============================================================================
\subsection{Necessary equipment}
\label{sec:prep-equip}
%==============================================================================
\let \oldlabelitemi=\labelitemi
\let \oldlabelitemii=\labelitemii
\let \oldlabelitemiii=\labelitemiii
\let \oldlabelitemiv=\labelitemiv
\renewcommand{\labelitemi}{$\square$}
\renewcommand{\labelitemii}{$\square$}
\renewcommand{\labelitemiii}{$\square$}
\renewcommand{\labelitemiv}{$\square$}
\begin{itemize}
\item \textbf{1x} Two-slot ELMA crate
\item \textbf{1x} CONV-TTL-RS485 device under test (DUT)
\item \textbf{1x} CONV-TTL-RTM-RS485
\item \textbf{1x} Pulse generator
\item \textbf{1x} Oscilloscope
\item \textbf{3x} Long LEMO 00 cables (1~m or more)
\item \textbf{5x} Short LEMO 00 cables (12~cm bridge cable or equivalent)
\item \textbf{4x} BNC male/ LEMO 00 female adapters
\item \textbf{3x} LEMO 00 "Y" splitter plug
\item \textbf{2x} LEMO 00 50~$\Omega$ terminations
\item \textbf{2x} LEMO 0S cables (at least 0.5~m in length)
\item \textbf{1x} LEMO 00 to 0S adapter
\end{itemize}
%==============================================================================
\subsection{Oscilloscope configuration}
\label{sec:prep-osc}
%==============================================================================
\begin{figure}[b]
\centerline{\includegraphics[width=\textwidth]{fig/IMG_2334.JPG}}
\caption{Oscilloscope connections}
\label{fig:osc-cfg}
\end{figure}
\begin{itemize}
\item \textbf{Trigger on the rising-edge of the external trigger channel}
\item Connect \textbf{1x BNC male / LEMO 00 female adapter} to the oscilloscope's \textbf{external trigger channel}
\item Connect \textbf{2x BNC male / LEMO 00 female adapters} to oscilloscope \textbf{channels 1 and 2}
\item Connect \textbf{2x LEMO 00 "Y" splitter plugs} to these BNC/LEMO 00 adapters
\item Connect \textbf{2x 50~$\Omega$ terminations} to one side of each LEMO 00 "Y" splitter
\end{itemize}
Note that any channel on the oscilloscope may be used, even though across this
document we use channels 1 and 2 (Figure~\ref{fig:osc-cfg}).
The trigger may also be set for another channel, it is not necessary to trigger
on the external channel.
%==============================================================================
\subsection{Pulse generator configuration}
\label{sec:prep-pulse-gen}
%==============================================================================
\begin{figure}
\centerline{\includegraphics[width=.5\textwidth]{fig/IMG_2330.JPG}}
\caption{Pulse generator connection}
\label{fig:pulse-gen-cfg}
\end{figure}
\begin{itemize}
\item Connect \textbf{1x BNC male / LEMO 00 female adapter} together with \textbf{1x LEMO 00 "Y" splitter plug}
to the \textbf{pulse generator's output}
\item Connect one side of the \textbf{LEMO 00 "Y" splitter plug} (the \textbf{oscilloscope trigger})
to the \textbf{oscilloscope's external trigger input} (Figure~\ref{fig:pulse-gen-cfg})
\item The other side (the \textbf{DUT trigger}) of the \textbf{LEMO 00 "Y" splitter plug} will be used to trigger
the DUT (Figure~\ref{fig:pulse-gen-cfg})
\item If the pulse generator is configurable, configure it as follows:
\begin{itemize}
\item 2~$\mu$s pulses
\item approx. 5~V on 50~$\Omega$ load
\item 1 Hz frequency
\end{itemize}
\item Turn on the pulse generator
\end{itemize}
%==============================================================================
\subsection{Board connections}
\label{sec:prep-board}
%==============================================================================
\begin{itemize}
\item Prepare the \textbf{two-slot ELMA crate}
\item Plug in the \textbf{CONV-TTL-RS485} in \textbf{slot 1} on the \textbf{front
part of the crate}, and the \textbf{RTM} in \textbf{slot 1} on the
\textbf{rear part of the crate}
\item Using \textbf{short LEMO 00 cables}, make a \textbf{daisy-chain} of the
\textbf{four INV-TTL channels} on the \textbf{front panel}
\begin{itemize}
\item \textbf{INV-TTL channel D OUT} to \textbf{INV-TTL channel C IN}
\item \textbf{INV-TTL channel C OUT} to \textbf{INV-TTL channel B IN}
\item \textbf{INV-TTL channel B OUT} to \textbf{INV-TTL channel A IN}
\item Plug a \textbf{long LEMO 00 cable} in the \textbf{INV-TTL channel A OUT}
connector
\end{itemize}
\item Connect \textbf{1x short LEMO 00 cable} to \textbf{1x LEMO 00 to LEMO 0S adapter}
\item Connect \textbf{1x short LEMO 0S cable} to the \textbf{0S side of the adapter}
\item This cable will be used to display the RS-485 signal on the oscilloscope
\item \textbf{Turn on the ELMA crate}
\item Download gateware version to be tested to the on-board flash
\end{itemize}
%==============================================================================
\subsection{Test scripts}
\label{sec:prep-test-scripts}
%==============================================================================
Some test scripts will need to be run across this test procedure. These
test scripts can be found in the \textit{software/} folder of the CONV-TTL-BLO
\textit{git} repository~\cite{ctb-repo}. One way to obtain this repository is
by running the following command in a Linux command line:
\begin{small}
\begin{center}
\verb+git clone --depth=1 git://ohwr.org/level-conversion/conv-ttl-blo.git+
\end{center}
\end{small}
%==============================================================================
% SEC: Test procedure
%==============================================================================
\pagebreak
\section{Test procedure}
\label{sec:procedure}
\let \oldlabelenumi=\labelenumi
\let \oldlabelenumii=\labelenumii
\let \oldlabelenumiii=\labelenumiii
\let \oldlabelenumiv=\labelenumiv
\renewcommand{\labelenumi}{\oldlabelenumi \ $\square$}
\renewcommand{\labelenumii}{\oldlabelenumii \ $\square$}
\renewcommand{\labelenumiii}{\oldlabelenumiii \ $\square$}
\renewcommand{\labelenumiv}{\oldlabelenumiv \ $\square$}
\renewcommand{\labelitemi}{\oldlabelitemi}
\renewcommand{\labelitemii}{\oldlabelitemii}
\renewcommand{\labelitemiii}{\oldlabelitemiii}
\renewcommand{\labelitemiv}{\oldlabelitemiv}
It is recommended to go through each of the following subsections in sequence
and follow the steps one by one, ticking on completion. If any error
appears, check your gateware and restart the procedure.
%==============================================================================
\subsection{TTL to RS485 pulse conversion}
\label{sec:proc-ttl-rs485}
%==============================================================================
\begin{enumerate}
\item Make sure the \textbf{TTL switch} (Figure~\ref{fig:switches}) of the CONV-TTL-RS485 is in the \textbf{TTL position (on)}
\item Make sure the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) is in the \textbf{OFF} position
\item \label{item:ttl-proc-start} Repeat the following steps for \textbf{all six channels}, \textbf{starting from channel 1} and fill in the
\textbf{table in Appendix~\ref{app:pulse-validation-ttl}}:
\begin{enumerate}
\item Connect the \textbf{DUT trigger} (see Section~\ref{sec:prep-pulse-gen}) to the \textbf{front panel INV-TTL channel D
input connector}
\item Connect \textbf{INV-TTL channel A OUT} to the \textbf{front panel channel input}
\item \label{item:ttl-meas-start} Connect the \textbf{front panel channel output} to \textbf{oscilloscope channel 1}
\item Connect \textbf{a rear panel channel output} to \textbf{oscilloscope channel 2}
\item \label{item:ttl-meas-ttl-out} Check that the characteristics of the signal
on \textbf{channel 1 of the oscilloscope} are as follows (Figure~\ref{fig:ttl-rs485}):
\begin{itemize}
\item 1.2~$\mu$s
\item approx. 3~V
\end{itemize}
\item If the signal characteristics are as above, \textbf{tick} the \textbf{TTL column for the channel} on the \textbf{Front panel} side
of the table in Appendix~\ref{app:pulse-validation-ttl}
\item \label{item:ttl-meas-rs485-out} Check that the characteristics of the signals at the
\textbf{rear panel} are as follows (Figure~\ref{fig:ttl-rs485}):
\begin{itemize}
\item approx. 1.2~$\mu$s
\item approx. 3~V
\end{itemize}
\item \label{item:ttl-meas-end} If the signal characteristics are as above, \textbf{tick} the \textbf{RS485} column for the channel
on the \textbf{Front panel} side of the table in Appendix~\ref{app:pulse-validation-ttl}
\end{enumerate}
\item Repeat the following steps for \textbf{channel 5 down to channel 1}:
\begin{enumerate}
\item Using a \textbf{short LEMO 0S cable}, connect \textbf{a channel 6 rear-panel output}
to the \textbf{rear panel channel input connector}
\item Perform \textbf{steps \ref{item:ttl-meas-start} to \ref{item:ttl-meas-end}}, this time
ticking the \textbf{TTL} and \textbf{RS485} columns on the \textbf{Rear panel} side of the
table in Appendix~\ref{app:pulse-validation-ttl}
\end{enumerate}
\item \label{item:ttl-proc-end} Test the \textbf{remaining rear panel channel 6 input} by this procedure:
\begin{enumerate}
\item Using a \textbf{LEMO 00 cable}, connect \textbf{INV-TTL channel A OUT} to \textbf{TTL channel 1 IN}
\item Using a \textbf{short LEMO 0S cable}, connect \textbf{rear panel channel 1 OUT} to \textbf{rear panel channel 6 IN}
\item Perform \textbf{steps \ref{item:ttl-meas-start} to \ref{item:ttl-meas-end}}, this time
ticking the \textbf{TTL} and \textbf{RS485} columns for \textbf{channel 6} on the \textbf{Rear panel} side of the
table in Appendix~\ref{app:pulse-validation-ttl}
\end{enumerate}
\item Turn off power to the ELMA crate
\item Change the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) to the \textbf{ON position}
\item Turn on power to the ELMA crate
\item Repeat \textbf{steps~\ref{item:ttl-proc-start}~to~\ref{item:ttl-proc-end}}, filling in the table in
\textbf{Appendix~\ref{app:pulse-validation-ttl-gf}}
\item Turn off power to the ELMA crate
\item Change the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) back to the \textbf{OFF position}
\end{enumerate}
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/switches}}
\caption{\label{fig:switches} \textbf{On-board switches}}
\end{figure}
\begin{figure}
\centerline{\includegraphics[width=.8\textwidth]{fig/ttl-rs485.png}}
\caption{TTL to RS485 conversion waveforms}
\label{fig:ttl-rs485}
\end{figure}
%==============================================================================
\pagebreak
\subsection{TTL-BAR to RS485 pulse conversion}
\label{sec:proc-ttlbar-rs485}
%==============================================================================
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/ttlbar-rs485.png}}
\caption{TTL-BAR to RS485 conversion waveforms}
\label{fig:ttlbar-rs485}
\end{figure}
\begin{enumerate}
\item Make sure the \textbf{TTL switch} (Figure~\ref{fig:switches}) of the CONV-TTL-RS485 is in the \textbf{TTL-BAR position (off)}
\item Make sure the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) is in the \textbf{OFF} position
\item \label{item:ttlbar-proc-start} Repeat the following steps for \textbf{all six channels}, \textbf{starting from channel 1} and fill in the
\textbf{table in Appendix~\ref{app:pulse-validation-ttlbar}}:
\begin{enumerate}
\item Connect the \textbf{DUT trigger} (see Section~\ref{sec:prep-pulse-gen}) to the \textbf{front panel INV-TTL channel C
input connector}
\item Connect \textbf{INV-TTL channel A OUT} to the \textbf{front panel channel input}
\item \label{item:ttlbar-meas-start} Connect the \textbf{front panel channel output} to \textbf{oscilloscope channel 1}
\item Connect \textbf{a rear panel channel output} to \textbf{oscilloscope channel 2}
\item \label{item:ttlbar-meas-ttl-out} Check that the characteristics of the signal
on \textbf{channel 1 of the oscilloscope} are as follows (Figure~\ref{fig:ttlbar-rs485}):
\begin{itemize}
\item 1.2~$\mu$s
\item approx. 3~V
\end{itemize}
\item If the signal characteristics are as above, \textbf{tick} the \textbf{TTL column for the channel} on the \textbf{Front panel} side
of the table in Appendix~\ref{app:pulse-validation-ttlbar}
\item \label{item:ttlbar-meas-rs485-out} Check that the characteristics of the signals at the
\textbf{rear panel} are as follows (Figure~\ref{fig:ttlbar-rs485}):
\begin{itemize}
\item approx. 1.2~$\mu$s
\item approx. 3~V
\end{itemize}
\item \label{item:ttlbar-meas-end} If the signal characteristics are as above, \textbf{tick} the \textbf{RS485} column for the channel
on the \textbf{Front panel} side of the table in Appendix~\ref{app:pulse-validation-ttlbar}
\end{enumerate}
\item Repeat the following steps for \textbf{channel 5 down to channel 1}:
\begin{enumerate}
\item Using a \textbf{short LEMO 0S cable}, connect \textbf{a channel 6 rear-panel output}
to the \textbf{rear panel channel input connector}
\item Perform \textbf{steps \ref{item:ttlbar-meas-start} to \ref{item:ttlbar-meas-end}}, this time
ticking the \textbf{TTL} and \textbf{RS485} columns on the \textbf{Rear panel} side of the
table in Appendix~\ref{app:pulse-validation-ttlbar}
\end{enumerate}
\item \label{item:ttlbar-proc-end} Test the \textbf{remaining rear panel channel 6 input} by this procedure:
\begin{enumerate}
\item Using a \textbf{LEMO 00 cable}, connect \textbf{INV-TTL channel A OUT} to \textbf{TTL channel 1 IN}
\item Using a \textbf{short LEMO 0S cable}, connect \textbf{rear panel channel 1 OUT} to \textbf{rear panel channel 6 IN}
\item Perform \textbf{steps \ref{item:ttlbar-meas-start} to \ref{item:ttlbar-meas-end}}, this time
ticking the \textbf{TTL} and \textbf{RS485} columns for \textbf{channel 6} on the \textbf{Rear panel} side of the
table in Appendix~\ref{app:pulse-validation-ttlbar}
\end{enumerate}
\item Turn off power to the ELMA crate
\item Change the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) to the \textbf{ON position}
\item Turn on power to the ELMA crate
\item Repeat \textbf{steps~\ref{item:ttlbar-proc-start}~to~\ref{item:ttlbar-proc-end}}, filling in the table in
\textbf{Appendix~\ref{app:pulse-validation-ttlbar-gf}}
\item Turn off power to the ELMA crate
\item Change the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) back to the \textbf{OFF position}
\end{enumerate}
%==============================================================================
\subsection{Power-on tests (TTL-BAR)}
\label{sec:proc-power-on-ttlbar}
%==============================================================================
\begin{enumerate}
\item Remove \textbf{all cables} from the \textbf{TTL and RS485 inputs and outputs}
\item Make sure the \textbf{TTL switch} (Figure~\ref{fig:switches}) is \textbf{OFF}
\item Make sure the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) is \textbf{OFF}
\item \label{item:ttlbar-poweron} Follow this procedure:
\begin{enumerate}
\item Configure the oscilloscope to trigger on the \textbf{falling edge} of the
\textbf{channel 1} input, at \textbf{approx. 2.5~V}
\item Connect the \textbf{output of TTL channel 1} to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
TTL-BAR output with an unconnected TTL-BAR input)
\item Turn off ELMA crate
\item Connect \textbf{1x short LEMO cable} from \textbf{INV-TTL channel A output} to
\textbf{TTL channel 6 input}
\item Connect the \textbf{output of TTL channel 6} to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
TTL-BAR output with a connected TTL-BAR input)
\item Turn off ELMA crate
\item Configure the oscilloscope to trigger on the \textbf{rising edge} of the
\textbf{channel 1} input
\item Connect \textbf{1x long LEMO 0S cable} from \textbf{RS485 output channel 1}
to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
RS485 output with an unconnected TTL-BAR input)
\item Turn off ELMA crate
\item Connect \textbf{1x long LEMO cable} from \textbf{RS485 output channel 6}
to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
RS485 output with a connected TTL-BAR input)
\item Turn off ELMA crate
\end{enumerate}
\item Flip the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) to the \textbf{ON position}
\item Follow the procedure in step~\ref{item:ttlbar-poweron}
\item Power-cycle the ELMA crate
\item Run the \textit{rdchxpcr.py} script (\textit{software/diag/rdchxpcr.py})
and confirm that all channel counters are 0
\item Run the \textit{rdtb.py} script (\textit{software/diag/timetag/rdtb.py})
and confirm that no pulses were stored to the timetag buffer
\item Turn off ELMA crate
\item Flip the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) back to the \textbf{OFF position}
\end{enumerate}
%==============================================================================
\subsection{Power-on tests (TTL)}
\label{sec:proc-power-on-ttl}
%==============================================================================
\begin{enumerate}
\item Remove \textbf{all cables} from the \textbf{TTL and RS485 inputs and outputs}
\item Put the \textbf{TTL switch} (Figure~\ref{fig:switches}) to the \textbf{ON} position
\item Make sure the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) is \textbf{OFF}
\item \label{item:ttl-poweron} Follow this procedure:
\begin{enumerate}
\item Configure the oscilloscope to trigger on the \textbf{rising edge} of the
\textbf{channel 1} input
\item Connect the \textbf{output of TTL channel 1} to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
TTL output with an unconnected TTL input)
\item Turn off ELMA crate
\item Connect \textbf{1x short LEMO cable} from \textbf{INV-TTL channel B output} to
\textbf{INV-TTL channel A input}
\item Connect \textbf{1x short LEMO cable} from \textbf{INV-TTL channel A} to
\textbf{TTL channel 6 input}
\item Connect the \textbf{output of TTL channel 6} to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
TTL output with a connected TTL input)
\item Turn off ELMA crate
\item Connect \textbf{1x long LEMO cable} from \textbf{RS485 output channel 1}
to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
RS485 output with an unconnected TTL input)
\item Turn off ELMA crate
\item Connect \textbf{1x long LEMO cable} from \textbf{RS485 output channel 6}
to \textbf{oscilloscope channel 1}
\item Turn on ELMA crate
\item Make sure the oscilloscope does not trigger (no pulse is generated on the
RS485 output with a connected TTL input)
\item Turn off ELMA crate
\end{enumerate}
\item Flip the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) to the \textbf{ON position}
\item Follow the procedure in step~\ref{item:ttl-poweron}
\item Power-cycle the ELMA crate
\item Run the \textit{rdchxpcr.py} script (\textit{software/diag/rdchxpcr.py})
and confirm that all channel counters are 0
\item Run the \textit{rdtb.py} script (\textit{software/diag/timetag/rdtb.py})
and confirm that no pulses were stored to the timetag buffer
\item Turn off ELMA crate
\item Flip the \textbf{glitch filter switch} (Figure~\ref{fig:switches}) back to the \textbf{OFF position}
\end{enumerate}
%==============================================================================
% APPENDICES
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: TTL pulse validation table
%==============================================================================
\section{Pulse conversion validation table (TTL, without glitch filter)}
\label{app:pulse-validation-ttl}
\centerline{
\resizebox{.8\textwidth}{!}{
\begin{tabular}{|l|*{2}{c}|*{2}{c}|}
\hline
\textbf{Input} & \multicolumn{2}{c|}{\textbf{Front panel}} & \multicolumn{2}{c|}{\textbf{Rear panel}} \\
\hline
\textbf{Output} & \textbf{TTL} & \textbf{RS485} & \textbf{TTL} & \textbf{RS485} \\
\hline
\textbf{CH1} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH2} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH3} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH4} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH5} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH6} & $\square$ & $\square$ & $\square$ & $\square$ \\
\hline
\end{tabular}
}
}
\vspace*{11pt}
Instructions for filling in the table:
\begin{itemize}
\item Following the test procedure in Section~\ref{sec:proc-ttl-rs485} (steps~\ref{item:ttl-proc-start}~to~\ref{item:ttl-proc-end}),
tick each box if the output is as expected
\item Tick the \textbf{TTL} boxes if the TTL output on the front panel is as specified
in step \ref{item:ttl-meas-ttl-out} (Section~\ref{sec:proc-ttl-rs485})
\item Tick the \textbf{RS485} boxes if the RS485 output on the rear panel
is as specified in step \ref{item:ttl-meas-rs485-out} (Section~\ref{sec:proc-ttl-rs485})
\end{itemize}
%==============================================================================
% APP: TTL pulse validation table, GF on
%==============================================================================
\pagebreak
\section{Pulse conversion validation table (TTL, with glitch filter)}
\label{app:pulse-validation-ttl-gf}
\centerline{
\resizebox{.8\textwidth}{!}{
\begin{tabular}{|l|*{2}{c}|*{2}{c}|}
\hline
\textbf{Input} & \multicolumn{2}{c|}{\textbf{Front panel}} & \multicolumn{2}{c|}{\textbf{Rear panel}} \\
\hline
\textbf{Output} & \textbf{TTL} & \textbf{RS485} & \textbf{TTL} & \textbf{RS485} \\
\hline
\textbf{CH1} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH2} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH3} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH4} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH5} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH6} & $\square$ & $\square$ & $\square$ & $\square$ \\
\hline
\end{tabular}
}
}
\vspace*{11pt}
Instructions for filling in the table:
\begin{itemize}
\item Make sure the glitch filter is \textbf{ON}
\item Following the test procedure in Section~\ref{sec:proc-ttl-rs485} (steps~\ref{item:ttl-proc-start}~to~\ref{item:ttl-proc-end}),
tick each box if the output is as expected
\item Tick the \textbf{TTL} boxes if the TTL output on the front panel is as specified
in step \ref{item:ttl-meas-ttl-out} (Section~\ref{sec:proc-ttl-rs485})
\item Tick the \textbf{RS485} boxes if the RS485 output on the rear panel
is as specified in step \ref{item:ttl-meas-rs485-out} (Section~\ref{sec:proc-ttl-rs485})
\end{itemize}
%==============================================================================
% APP: TTL-BAR pulse validation table
%==============================================================================
\pagebreak
\section{Pulse conversion validation table (TTL-BAR, without glitch filter)}
\label{app:pulse-validation-ttlbar}
\centerline{
\resizebox{.8\textwidth}{!}{
\begin{tabular}{|l|*{2}{c}|*{2}{c}|}
\hline
\textbf{Input} & \multicolumn{2}{c|}{\textbf{Front panel}} & \multicolumn{2}{c|}{\textbf{Rear panel}} \\
\hline
\textbf{Output} & \textbf{TTL} & \textbf{RS485} & \textbf{TTL} & \textbf{RS485} \\
\hline
\textbf{CH1} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH2} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH3} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH4} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH5} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH6} & $\square$ & $\square$ & $\square$ & $\square$ \\
\hline
\end{tabular}
}
}
\vspace*{11pt}
Instructions for filling in the table:
\begin{itemize}
\item Following the test procedure in Section~\ref{sec:proc-ttlbar-rs485}
(steps~\ref{item:ttlbar-proc-start}~to~\ref{item:ttlbar-proc-end}), tick each box if the output
is as expected
\item Tick the \textbf{TTL} boxes if the TTL output on the front panel is as specified
in step \ref{item:ttlbar-meas-ttl-out} (Section~\ref{sec:proc-ttlbar-rs485})
\item Tick the \textbf{RS485} boxes if the RS485 output on the rear panel
is as specified in step \ref{item:ttlbar-meas-rs485-out} (Section~\ref{sec:proc-ttlbar-rs485})
\end{itemize}
%==============================================================================
% APP: TTL-BAR pulse validation table, GF on
%==============================================================================
\pagebreak
\section{Pulse conversion validation table (TTL-BAR, with glitch filter)}
\label{app:pulse-validation-ttlbar-gf}
\centerline{
\resizebox{.8\textwidth}{!}{
\begin{tabular}{|l|*{2}{c}|*{2}{c}|}
\hline
\textbf{Input} & \multicolumn{2}{c|}{\textbf{Front panel}} & \multicolumn{2}{c|}{\textbf{Rear panel}} \\
\hline
\textbf{Output} & \textbf{TTL} & \textbf{RS485} & \textbf{TTL} & \textbf{RS485} \\
\hline
\textbf{CH1} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH2} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH3} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH4} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH5} & $\square$ & $\square$ & $\square$ & $\square$ \\
\textbf{CH6} & $\square$ & $\square$ & $\square$ & $\square$ \\
\hline
\end{tabular}
}
}
\vspace*{11pt}
Instructions for filling in the table:
\begin{itemize}
\item Make sure the glitch filter is \textbf{ON}
(steps~\ref{item:ttlbar-proc-start}~to~\ref{item:ttlbar-proc-end}), tick each box if the output
is as expected
\item Tick the \textbf{TTL} boxes if the TTL output on the front panel is as specified
in step \ref{item:ttlbar-meas-ttl-out} (Section~\ref{sec:proc-ttlbar-rs485})
\item Tick the \textbf{RS485} boxes if the RS485 output on the rear panel
is as specified in step \ref{item:ttlbar-meas-rs485-out} (Section~\ref{sec:proc-ttlbar-rs485})
\end{itemize}
\end{appendices}
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{gw-test-procedure}
\addcontentsline{toc}{section}{References}
\end{document}
doc/hdlg/Makefile 0 → 100644
View file @ 3395277e
FILE=hdlg-conv-ttl-rs485
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/hdlg/README 0 → 100644
View file @ 3395277e
To work with the template:
1. Copy to location of choice
2. Run the 'getstarted' script, which will:
- ask you for the file names (you give it <fname>, NO extensions, please)
- ask you for the document title
- change doc.* to <fname>.*
- add <fname> to the appropriate location in the Makefile
- change the <fname>.tex file to include <fname>.bib as bibliography
- change the title in cern-title.tex
3. Delete the 'getstarted' script
4. Write your documentation
5. Type 'make' to create your .pdf documentation file.
NOTE: You need Inkscape to generate .pdf files for the figures:
sudo apt-get install inkscape
doc/hdlg/cern-title.tex 0 → 100644
View file @ 3395277e
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{CONV-TTL-RS485 HDL Guide}}
\noindent \rule{\textwidth}{.1cm}
\hfill August 12, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/hdlg/fig/Makefile 0 → 100644
View file @ 3395277e
SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
doc/hdlg/fig/block-diagram.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="550.60352"
height="247"
id="svg2"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="block-diagram.svg">
<defs
id="defs4">
<marker
inkscape:stockid="TriangleInM"
orient="auto"
refY="0"
refX="0"
id="TriangleInM"
style="overflow:visible">
<path
id="path5051"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(-0.4,-0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path3992"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="3.959798"
inkscape:cx="208.93153"
inkscape:cy="118.66757"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
showguides="true"
inkscape:guide-bbox="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0">
<inkscape:grid
type="xygrid"
id="grid2985"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="-113.63672px"
originy="-739px" />
<sodipodi:guide
orientation="1,0"
position="-363.63672,331"
id="guide2987" />
</sodipodi:namedview>
<metadata
id="metadata7">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-113.63672,-66.362183)">
<g
id="g5717">
<rect
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3779"
width="80"
height="35"
x="190"
y="77.362183" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="230.16113"
y="91.217163"
id="text3769"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="230.16113"
y="91.217163"
id="tspan3773"
style="font-size:10px;text-align:center;text-anchor:middle">TTL/TTL-BAR</tspan><tspan
id="tspan3777"
sodipodi:role="line"
x="230.16113"
y="103.71716"
style="font-size:10px;text-align:center;text-anchor:middle">input logic</tspan></text>
</g>
<g
id="g4084"
transform="translate(0,30)">
<rect
y="77.362183"
x="505"
height="35"
width="80"
id="rect3799"
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text3801"
y="91.217163"
x="545.16113"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan3803"
y="91.217163"
x="545.16113"
sodipodi:role="line">TTL/TTL-BAR</tspan><tspan
style="font-size:10px;text-align:center;text-anchor:middle"
y="103.71716"
x="545.16113"
sodipodi:role="line"
id="tspan3805">output logic</tspan></text>
</g>
<g
id="g4090"
transform="translate(0,30)">
<rect
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3807"
width="80"
height="35"
x="505"
y="132.36218" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="545.16113"
y="146.21716"
id="text3809"
sodipodi:linespacing="125%"><tspan
id="tspan3813"
sodipodi:role="line"
x="545.16113"
y="146.21716"
style="font-size:10px;text-align:center;text-anchor:middle">Pulse LED</tspan><tspan
id="tspan3817"
sodipodi:role="line"
x="545.16113"
y="158.71716"
style="font-size:10px;text-align:center;text-anchor:middle">logic</tspan></text>
</g>
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 289.19685,113.76113 c 5.16063,6.88084 5.16063,10.32125 0,17.20209 12.04146,0 20.64251,0 25.80315,-8.60104 -5.16064,-8.60105 -13.76169,-8.60105 -25.80315,-8.60105 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 275,95.362183 5,0 0,21.999997 5,0"
id="path5544"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 275,149.36218 5,0 0,-22 5,0"
id="path5546"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 320,122.36218 10,0"
id="path3838"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 480,122.36218 20,0"
id="path4096"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 160,95.362183 25,0"
id="path4284"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path4470"
d="m 160,149.36218 25,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="140"
y="94.362183"
id="text4472"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4474"
x="140"
y="94.362183"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle">TTL input</tspan><tspan
sodipodi:role="line"
x="140"
y="101.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan4476">(front pan.)</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4478"
y="147.36218"
x="135"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
y="147.36218"
x="135"
id="tspan4480"
sodipodi:role="line">RS-485 input</tspan><tspan
id="tspan4482"
style="font-size:6px;text-align:center;text-anchor:middle"
y="154.86218"
x="135"
sodipodi:role="line">(rear pan.)</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4484"
y="121.36218"
x="635"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
y="121.36218"
x="635"
id="tspan4486"
sodipodi:role="line">TTL output</tspan><tspan
id="tspan4488"
style="font-size:6px;text-align:center;text-anchor:middle"
y="128.86218"
x="635"
sodipodi:role="line">(front pan.)</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="640"
y="149.36218"
id="text4490"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4492"
x="640"
y="149.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle">RS-485 output</tspan><tspan
sodipodi:role="line"
x="640"
y="156.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan4494">(rear pan.)</tspan></text>
<path
inkscape:connector-curvature="0"
id="path4496"
d="m 590,122.36218 20,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:none;marker-end:url(#marker3062)"
d="m 490,122.36218 0,30 120,0"
id="path4498"
inkscape:connector-curvature="0" />
<g
id="g4887"
transform="translate(0,85)">
<rect
y="132.36218"
x="505"
height="35"
width="80"
id="rect4889"
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text4891"
y="146.21716"
x="545.16113"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;text-align:center;text-anchor:middle"
y="146.21716"
x="545.16113"
sodipodi:role="line"
id="tspan4895">Bicolor LED</tspan><tspan
style="font-size:10px;text-align:center;text-anchor:middle"
y="158.71716"
x="545.16113"
sodipodi:role="line"
id="tspan4899">logic</tspan></text>
</g>
<path
inkscape:connector-curvature="0"
id="path4901"
d="m 480,182.36218 20,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 480,234.36218 20,0"
id="path4907"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path4909"
d="m 160,292.36218 200,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInM);marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 590,182.36218 20,0"
id="path5359"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="635"
y="177.36218"
id="text5361"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan5363"
x="635"
y="177.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle">Pulse LEDs</tspan><tspan
sodipodi:role="line"
x="635"
y="184.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan5365">(front and</tspan><tspan
sodipodi:role="line"
x="635"
y="192.36218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan5367">rear pan.)</tspan></text>
<path
inkscape:connector-curvature="0"
id="path5371"
d="m 590,234.36218 20,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<text
sodipodi:linespacing="125%"
id="text5373"
y="232.36218"
x="635"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
y="232.36218"
x="635"
id="tspan5375"
sodipodi:role="line">Bicolor LEDs</tspan><tspan
id="tspan5379"
style="font-size:6px;text-align:center;text-anchor:middle"
y="239.86218"
x="635"
sodipodi:role="line">(front pan.)</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="140"
y="287.36218"
id="text5383"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan5385"
x="140"
y="287.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle">I<tspan
style="font-size:65.00091553%;baseline-shift:super"
id="tspan5391">2</tspan>C</tspan><tspan
sodipodi:role="line"
x="140"
y="294.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan5387">(VME P1)</tspan></text>
<path
inkscape:connector-curvature="0"
id="path5393"
d="m 480,272.36218 130,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInM);marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<text
sodipodi:linespacing="125%"
id="text5581"
y="272.36218"
x="640"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
y="272.36218"
x="640"
id="tspan5583"
sodipodi:role="line">SPI</tspan><tspan
id="tspan5587"
style="font-size:6px;text-align:center;text-anchor:middle"
y="279.86218"
x="640"
sodipodi:role="line">(on-board flash)</tspan></text>
<rect
style="fill:none;stroke:#000000;stroke-width:2;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3921"
width="430"
height="245"
x="170"
y="67.362183" />
<path
transform="matrix(2,0,0,2,574.78516,119.80416)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path3894"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5607"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,574.78516,92.804161)" />
<path
transform="matrix(2,0,0,2,574.78516,67.804161)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5609"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5611"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,574.78516,37.804161)" />
<path
transform="matrix(2,0,0,2,574.78516,7.804161)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5613"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5615"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,144.78516,-19.195839)" />
<path
transform="matrix(2,0,0,2,144.78516,34.804161)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5617"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5619"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,144.78516,177.80416)" />
<g
id="g5723">
<rect
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect5623"
width="80"
height="35"
x="190.15625"
y="132.36218" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="230"
y="146.28308"
id="text5625"
sodipodi:linespacing="125%"><tspan
id="tspan5627"
sodipodi:role="line"
x="230"
y="146.28308"
style="font-size:10px;text-align:center;text-anchor:middle">RS-485</tspan><tspan
sodipodi:role="line"
x="230"
y="158.78308"
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan5629">input logic</tspan></text>
</g>
<g
id="g5693"
transform="translate(4.9999988,0)">
<rect
y="187.36218"
x="185"
height="35"
width="80"
id="rect5655"
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text5657"
y="201.28308"
x="224.84375"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;text-align:center;text-anchor:middle"
y="201.28308"
x="224.84375"
sodipodi:role="line"
id="tspan5659">Line</tspan><tspan
id="tspan5661"
style="font-size:10px;text-align:center;text-anchor:middle"
y="213.78308"
x="224.84375"
sodipodi:role="line">input logic</tspan></text>
</g>
<g
id="g5699"
transform="translate(5.1562488,0)">
<rect
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect5663"
width="80"
height="35"
x="185"
y="242.36218" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="224.84375"
y="256.28308"
id="text5665"
sodipodi:linespacing="125%"><tspan
id="tspan5667"
sodipodi:role="line"
x="224.84375"
y="256.28308"
style="font-size:10px;text-align:center;text-anchor:middle">Switch</tspan><tspan
sodipodi:role="line"
x="224.84375"
y="268.78308"
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan5669">input logic</tspan></text>
</g>
<path
inkscape:connector-curvature="0"
id="path5675"
d="m 160,262.36218 25,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<path
transform="matrix(2,0,0,2,144.78516,147.80416)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5677"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="140"
y="262.36218"
id="text5679"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan5681"
x="140"
y="262.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle">Switches</tspan><tspan
sodipodi:role="line"
x="140"
y="269.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan5683">(on board)</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 66.36328,29 0,102 4.999999,0"
id="path5729"
inkscape:connector-curvature="0"
transform="translate(113.63672,66.362183)"
sodipodi:nodetypes="ccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 61.36328,83 0,63 9.999999,0"
id="path5731"
inkscape:connector-curvature="0"
transform="translate(113.63672,66.362183)"
sodipodi:nodetypes="ccc" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 275,262.36218 85,0"
id="path5919"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path5921"
d="m 275,205.36218 85,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<g
id="g5256"
transform="translate(24.975586,0)">
<rect
y="77.362183"
x="340"
height="225"
width="110"
id="rect2989"
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text3759"
y="92.362183"
x="395.02441"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan3763"
y="92.362183"
x="395.02441"
sodipodi:role="line">Converter board</tspan><tspan
style="font-size:10px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan3767"
y="104.86218"
x="395.02441"
sodipodi:role="line">common gateware</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4024"
y="123.36218"
x="448"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="123.36218"
x="448"
id="tspan4026"
sodipodi:role="line">pulse_o</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="342"
y="123.36218"
id="text4028"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4030"
x="342"
y="123.36218"
style="font-size:6px;text-align:start;text-anchor:start">pulse_i</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4903"
y="183.36218"
x="448"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="183.36218"
x="448"
id="tspan4905"
sodipodi:role="line">led_pulse_o</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="448"
y="272.36218"
id="text3928"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3930"
x="448"
y="272.36218"
style="font-size:6px;text-align:end;text-anchor:end">spi_cs_n_o</tspan><tspan
id="tspan3934"
sodipodi:role="line"
x="448"
y="279.86218"
style="font-size:6px;text-align:end;text-anchor:end">spi_sclk_o</tspan><tspan
id="tspan3938"
sodipodi:role="line"
x="448"
y="287.36218"
style="font-size:6px;text-align:end;text-anchor:end">spi_mosi_o</tspan><tspan
id="tspan3936"
sodipodi:role="line"
x="448"
y="294.86218"
style="font-size:6px;text-align:end;text-anchor:end">spi_miso_i</tspan><tspan
id="tspan3942"
sodipodi:role="line"
x="448"
y="302.36218"
style="font-size:6px;text-align:end;text-anchor:end" /></text>
<text
sodipodi:linespacing="125%"
id="text3944"
y="227.36218"
x="448"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="227.36218"
x="448"
id="tspan3946"
sodipodi:role="line">spi_cs_n_o</tspan><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="234.86218"
x="448"
sodipodi:role="line"
id="tspan3948">spi_sclk_o</tspan><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="242.36218"
x="448"
sodipodi:role="line"
id="tspan3950">spi_mosi_o</tspan><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="249.86218"
x="448"
sodipodi:role="line"
id="tspan3952">spi_miso_i</tspan><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="257.36218"
x="448"
sodipodi:role="line"
id="tspan3954" /></text>
<text
sodipodi:linespacing="125%"
id="text3970"
y="204.36218"
x="342"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:start;text-anchor:start"
y="204.36218"
x="342"
id="tspan3972"
sodipodi:role="line">line_front_i,</tspan><tspan
id="tspan3976"
style="font-size:6px;text-align:start;text-anchor:start"
y="211.86218"
x="342"
sodipodi:role="line">etc.</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="342"
y="262.36218"
id="text3984"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3986"
x="342"
y="262.36218"
style="font-size:6px;text-align:start;text-anchor:start">sw_gp_i,</tspan><tspan
sodipodi:role="line"
x="342"
y="269.86218"
style="font-size:6px;text-align:start;text-anchor:start"
id="tspan3988">sw_multicast_i</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3990"
y="290.36218"
x="342"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan3994"
style="font-size:6px;text-align:start;text-anchor:start"
y="290.36218"
x="342"
sodipodi:role="line">scl,</tspan><tspan
id="tspan4009"
style="font-size:6px;text-align:start;text-anchor:start"
y="297.86218"
x="342"
sodipodi:role="line">sda</tspan></text>
</g>
<rect
style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect5291"
width="9.84375"
height="35"
x="335.15625"
y="103.44128" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="335"
y="152.36218"
id="text5293"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="335"
y="152.36218"
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan5297">First pulse</tspan><tspan
id="tspan5301"
sodipodi:role="line"
x="335"
y="164.86218"
style="font-size:10px;text-align:center;text-anchor:middle">inhibit</tspan></text>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path5305"
d="m 350,122.36218 10,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)" />
</g>
</svg>
doc/hdlg/fig/cern-logo.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="utf-8"?>
<!-- Generator: Adobe Illustrator 15.0.2, SVG Export Plug-In . SVG Version: 6.00 Build 0) -->
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
width="184.252px" height="184.252px" viewBox="0 0 184.252 184.252" enable-background="new 0 0 184.252 184.252"
xml:space="preserve">
<g>
<path fill="#0053A1" d="M38.544,76.536c-0.921,0.7-4.123,2.692-8.941,2.692c-8.718,0-14.658-5.495-14.658-13.872
c0-8.328,6.298-13.87,14.862-13.87c3.332,0,7.147,1.026,9.275,1.939c-0.445,0.985-0.811,2.286-0.965,3.1l-0.233,0.077
c-1.647-1.823-4.295-3.402-8.213-3.402c-4.972,0-10.696,4.027-10.696,12.056c0,7.819,5.832,11.974,11.046,11.974
c4.684,0,6.927-2.186,8.939-3.885l0.154,0.154L38.544,76.536z"/>
<path fill="#0053A1" d="M60.139,77.312c0-0.588,0.05-1.193,0.092-1.487c-2.644,0.243-9.903,0.463-12.734,0.504
c-0.048-0.707-0.11-9.091-0.04-10.387c1.132,0,7.114,0.078,9.787,0.35c-0.077-0.388-0.116-0.962-0.116-1.35
c0-0.387,0.039-1.082,0.116-1.469c-2.286,0.193-5.214,0.387-9.787,0.387c0-0.969,0.079-8.037,0.118-9.701
c5.036,0,9.596,0.313,12.148,0.504c-0.042-0.264-0.092-0.807-0.092-1.337c0-0.528,0.035-0.958,0.092-1.322
c-1.342,0.09-5.678,0.195-8.003,0.195c-2.324,0-5.913-0.078-8.237-0.195c0.154,3.294,0.311,6.664,0.311,9.997v6.664
c0,3.333-0.156,6.704-0.311,10.075c2.363-0.117,5.99-0.194,8.354-0.194c0.111,0,0.227,0,0.343,0
c0.81,0.003,1.835,0.014,2.893,0.033c1.833,0.034,3.767,0.089,5.159,0.161l0,0l0,0C60.173,78.331,60.139,77.899,60.139,77.312z"/>
<path fill="#0053A1" d="M68.815,65.622v3.082c0,3.332,0.154,6.701,0.311,10.034c-0.66-0.117-1.852-0.128-2.096-0.128
c-0.243,0-1.435,0.012-2.094,0.128c0.155-3.333,0.31-6.703,0.31-10.034v-6.666c0-3.332-0.155-6.703-0.31-10.035
c1.473,0.117,3.336,0.195,4.809,0.195c1.473,0,2.945-0.195,4.417-0.195c4.379,0,8.39,1.293,8.39,6.169
c0,5.161-5.14,7.013-8.085,7.401c1.899,2.363,8.7,10.646,10.947,13.165c-0.774-0.117-2.073-0.128-2.427-0.128
c-0.354,0-1.691,0.012-2.427,0.128c-1.531-2.335-6.437-9.686-9.77-13.117C70.688,65.621,68.815,65.622,68.815,65.622z
M71.411,64.204c3.199-0.065,7.4-1.081,7.4-5.502c0-3.852-3.371-5.076-6.005-5.076c-1.782,0-2.945,0.116-3.758,0.193
c-0.117,2.829-0.232,5.428-0.232,8.218c0,0,0,1.851,0,2.131C69.2,64.221,71.016,64.21,71.411,64.204z"/>
<path fill="#0053A1" d="M112.594,51.99c-0.453,0.078-1.013,0.142-1.699,0.142c-0.676,0-1.257-0.073-1.651-0.142
c0.17,3.174,0.462,9.047,0.462,12.899c0,2.898,0,5.428-0.04,6.862c-1.409-1.499-17.576-18.23-19.219-20.016l-1.269-0.013
c0.057,2.465,0.129,5.141,0.129,10.022c0,6.249-0.087,12.896-0.406,16.994c0.453-0.079,1.012-0.142,1.698-0.142
c0.677,0,1.257,0.071,1.65,0.142c-0.169-3.173-0.461-9.048-0.461-12.898c0-2.899,0.002-5.882,0.041-7.314
c1.409,1.5,17.667,18.458,19.218,20.561l1.269,0.012c-0.058-2.465-0.129-5.234-0.129-10.116
C112.187,62.734,112.275,56.085,112.594,51.99z"/>
<path fill="#0053A1" d="M42.069,121.789c-7.614-12.048-9.781-23.679-10.084-32.58c-1.173,0-2.346,0-3.519,0
c0.295,9.71,2.65,19.893,7.919,29.872C37.627,120.083,40.544,121.358,42.069,121.789z"/>
<path fill="#0053A1" d="M184.25,1.679c0,0-87.554-0.694-115.47-0.679c-4.369,0.003-7.302,0.311-8.248,0.371
C26.048,3.605,0.115,33.842,0,66.817c-0.032,9.586,2.522,20.39,6.667,34.973c5.476,19.267,11.891,41.367,11.891,41.367h3.499
L9.128,99.539l0.097-0.065c9.497,18.347,31.392,33.086,56.237,33.086c13.407,0,25.841-3.753,35.638-10.666l0.085,0.08
l-57.516,61.204h4.492c0,0,40.387-42.968,54.125-57.556c10.527-11.178,15.996-18.381,18.285-22.119
c2.625-4.287,10.964-16.645,10.652-34.847l0.112-0.008l25.203,114.529h3.618c0,0-21.146-93.744-25.25-113.349
c-4.038-19.292-8.809-31.258-13.957-38.083c-1.769-0.985-4.527-2.107-5.828-2.411c7.472,9.428,13.055,23.454,13.055,37.489
c0,34.355-27.95,62.304-62.306,62.304c-34.354,0-62.304-27.949-62.304-62.304c0-34.356,28.05-62.306,62.324-62.306
c15.235,0,29.356,5.588,40.209,14.79c2.098,0.29,4.91,0.945,6.589,1.551l0.013-0.035C104.902,13.046,95.163,7.265,84.33,4.225
c0-0.084,0-0.089,0-0.089l99.922,0.623L184.25,1.679z"/>
<path fill="#0053A1" d="M50.808,132.873c-2.228-0.329-5.011-1.118-6.685-1.836c7.5,8.536,17.82,15.366,27.953,19.198l2.659-2.821
C63.744,143.702,55.756,137.737,50.808,132.873"/>
<path fill="#0053A1" d="M142.469,127.885c-11.121,13.615-28.388,22.783-48.226,22.771c-4.259-0.001-8.391-0.478-11.836-1.179
l-2.847,3.022c5.445,1.258,10.271,1.731,14.885,1.731c20.405,0,37.861-9.523,48.972-22.057L142.469,127.885"/>
<path fill="#0053A1" d="M165.644,17.304l-6.001,61.965h-0.113c-0.851-11.696-6.682-25.666-13.883-34.498
c-12.5-15.329-30.842-24.585-51.444-24.585c-19.647,0-37.15,8.717-49.192,22.381l2.758,2.186
C59.145,31.888,75.442,23.643,94.2,23.643c22.836,0,41.439,11.704,51.845,27.615c9.286,14.197,12.365,32.39,10.213,45.719
c-0.727,4.502-2.36,13.257-8.359,23.176l1.05,4.614c7.358-11.405,11.091-21.556,14.005-47.503
c2.234-19.906,6.073-59.962,6.073-59.962L165.644,17.304z"/>
</g>
</svg>
doc/hdlg/fig/first-pulse-inhibit.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="331.05316"
height="96"
id="svg3876"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="first-pulse-inhibit.svg">
<defs
id="defs3878">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path4730"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="145.76561"
inkscape:cy="-2.0634765"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
showguides="true"
inkscape:guide-bbox="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0">
<inkscape:grid
type="xygrid"
id="grid4392"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="-23.94685px"
originy="-899.5px" />
</sodipodi:namedview>
<metadata
id="metadata3881">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-23.94685,-56.862183)">
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 140.86614,83.93695 -44.29133,0 0,-17.71653 -26.57481,0"
id="path16881"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 96.57481,66.22042 141.73228,0"
id="path16883"
inkscape:connector-curvature="0" />
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 238.30709,60.90547 c 0,8.85825 0,8.85825 0,17.71652 12.04146,0 17.71654,-3.5433 17.71654,-8.85827 0,-5.31496 -5.67508,-8.85825 -17.71654,-8.85825 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 140.86615,133.54325 -26.57481,0"
id="path4566"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="translate(-13.408429,82.93692)"
d="m 111.75489,-16.716501 a 1.7716535,1.7716535 0 1 1 -3.54331,0 1.7716535,1.7716535 0 1 1 3.54331,0 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path4618"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.56;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<text
sodipodi:linespacing="125%"
id="text4622"
y="135.36218"
x="113"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="135.36218"
x="113"
sodipodi:role="line"
id="tspan3013"
style="font-size:6px;text-align:end;text-anchor:end">20 MHz</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 202.87402,83.93695 17.71653,0 0,-10.62992 17.71654,0"
id="path16971"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 256.02362,69.76372 8.85827,0"
id="path16973"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="translate(29.111253,116.59834)"
d="m 111.75489,-16.716501 a 1.7716535,1.7716535 0 1 1 -3.54331,0 1.7716535,1.7716535 0 1 1 3.54331,0 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path3020"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<rect
style="opacity:0.98999999;fill:#000000;fill-opacity:0.1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect16159"
width="62.007866"
height="70.866119"
x="140.86615"
y="75.07869" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 140.86614,128.22829 7.92662,5.2844 -7.92662,5.34552"
id="path4425"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="142.6378"
y="87.480263"
id="text16885"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan16887"
x="142.6378"
y="87.480263">cnt</tspan></text>
<text
sodipodi:linespacing="125%"
id="text16889"
y="87.480263"
x="178.07086"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="87.480263"
x="178.07086"
id="tspan16891"
sodipodi:role="line">en_o</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3010"
y="119.37003"
x="170.98425"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="119.37003"
x="170.98425"
id="tspan3012"
sodipodi:role="line"
style="font-size:12px;font-weight:bold;text-align:center;text-anchor:middle">&lt;1999</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3012"
y="103.42514"
x="142.6378"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="103.42514"
x="142.6378"
id="tspan3014"
sodipodi:role="line">rst</tspan></text>
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path3936-1"
d="m 24.19685,57.761133 c 5.16063,6.88084 5.16063,10.32125 0,17.20209 12.04146,0 20.64251,0 25.80315,-8.60104 -5.16064,-8.60105 -13.76169,-8.60105 -25.80315,-8.60105 z"
style="opacity:0.3;fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path3838"
d="m 55,66.362183 10.000001,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)" />
<rect
y="57.362183"
x="295"
height="95"
width="60"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m 295,57.362183 0,94.999997"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 115,99.88183 22.32284,0"
id="path3790"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="206.41733"
y="92.795258"
id="text3017"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3019"
x="206.41733"
y="92.795258"
style="font-size:6px">en_o = '0'</tspan><tspan
sodipodi:role="line"
x="206.41733"
y="100.29526"
id="tspan3025"
style="font-size:6px"><tspan
style="font-size:6px;font-weight:bold"
id="tspan3027">if</tspan> cnt &lt; 1999</tspan><tspan
sodipodi:role="line"
x="206.41733"
y="107.79526"
style="font-size:6px"
id="tspan3825">(line low for</tspan><tspan
sodipodi:role="line"
x="206.41733"
y="115.29526"
style="font-size:6px"
id="tspan3827">100 us)</tspan></text>
<rect
y="57.362183"
x="70"
height="93.897598"
width="194.8819"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:6, 2;stroke-dashoffset:0"
rx="8.858223"
ry="8.858223" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 270,69.76374 21.4567,0"
id="path3036"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="113"
y="101.36218"
id="text4465"
sodipodi:linespacing="125%"><tspan
style="font-size:6px;text-align:end;text-anchor:end"
id="tspan4467"
sodipodi:role="line"
x="113"
y="101.36218">rst_n</tspan></text>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4914"
d="m 270,69.76374 21.4567,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="300"
y="73.362183"
id="text4969"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4971"
x="300"
y="73.362183">pulse_i</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4973"
y="122.36218"
x="300"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="122.36218"
x="300"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold">Conv.</tspan><tspan
y="134.86218"
x="300"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold">common</tspan><tspan
y="147.36218"
x="300"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold">gateware</tspan></text>
</g>
</svg>
doc/hdlg/fig/line-inp.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="248.78418"
height="107"
id="svg4040"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="line-inp.svg">
<defs
id="defs4042">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path3992"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker4023"
style="overflow:visible">
<path
id="path4025"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-9"
style="overflow:visible">
<path
id="path4441"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-6"
style="overflow:visible">
<path
id="path3992-3"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker5356"
style="overflow:visible">
<path
id="path5358"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3133"
style="overflow:visible">
<path
id="path3135"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="7.919596"
inkscape:cx="125.48947"
inkscape:cy="2.0659949"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="true"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid4556"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="-91.21582px"
originy="-859px" />
</sodipodi:namedview>
<metadata
id="metadata4045">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-91.21582,-86.362183)">
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 215,167.36218 35,0"
id="path4051"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="m 195,87.362183 0,104.999997"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="200"
y="102.36218"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="200"
y="102.36218"
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="102.36218"
x="190"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end;opacity:0.3"
y="102.36218"
x="190"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<text
sodipodi:linespacing="125%"
id="text5499"
y="166.36218"
x="111"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="166.36218"
x="111"
sodipodi:role="line"
id="tspan5525">TTL, INVTTL</tspan><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="173.86218"
x="111"
sodipodi:role="line"
id="tspan4137">or RS485 line</tspan></text>
<rect
y="87.362183"
x="270"
height="104.99999"
width="70"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m 270,87.362183 0,104.999997"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<text
sodipodi:linespacing="125%"
id="text4973"
y="102.36218"
x="275"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="102.36218"
x="275"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold">Conv.</tspan><tspan
y="114.86218"
x="275"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold">common</tspan><tspan
y="127.36218"
x="275"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold">gateware</tspan></text>
<g
id="g3909">
<rect
y="162.36218"
x="273"
height="13"
width="23"
id="rect3897"
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="274.93604"
y="172.50232"
id="text3893"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3895"
x="274.93604"
y="172.50232">LSR</tspan></text>
</g>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)"
d="m 255,167.36218 10,0"
id="path3918"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<rect
y="152.36218"
x="215"
height="29.999987"
width="35.000076"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:3, 1;stroke-dashoffset:2.15"
rx="5"
ry="5" />
<g
transform="matrix(0.61914096,0,0,0.61914096,137.89186,92.772793)"
id="g3783"
style="fill:#ffffff;fill-opacity:1">
<path
inkscape:connector-curvature="0"
id="path3785"
d="m 141.73228,113.3858 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
transform="matrix(0.24999996,0,0,0.24999996,121.67006,91.240144)"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
sodipodi:ry="7.0866141"
sodipodi:rx="7.0866141"
sodipodi:cy="116.92912"
sodipodi:cx="159.44882"
id="path3787"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
</g>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 158.12063,167.36218 36.87937,0"
id="path4057"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.30957049;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 144.95779,162.97463 0,10.96899 10.96899,-6.58139 -10.96899,-6.58139 z"
id="path3757"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:2.00000858;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path3759"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.15478457,0,0,0.15478457,132.5365,149.26341)" />
<g
id="g3611"
transform="matrix(0.21125073,0,0,0.21125073,143.74324,122.07639)"
style="opacity:0.3;stroke:#000000;stroke-width:1.46541727;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none">
<path
transform="translate(-15.675442,33.433089)"
inkscape:connector-curvature="0"
id="path3607"
d="m 29.848669,186.25198 10.629922,0 3.543307,-10.62992 7.086614,0"
style="fill:none;stroke:#000000;stroke-width:1.46541727;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="fill:none;stroke:#000000;stroke-width:1.46541727;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 35.43307,209.05515 -10.629922,0 -3.543307,10.62992 -7.086614,0"
id="path3609"
inkscape:connector-curvature="0" />
</g>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4176"
d="m 135,167.36218 10,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="opacity:0.5;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:1.5, 1.5;stroke-dashoffset:1.6;marker-end:url(#marker3133)"
d="m 110.41797,136 0,-25 120,0 0,20"
id="path4178"
inkscape:connector-curvature="0"
transform="translate(29.582031,31.362183)"
sodipodi:nodetypes="cccc" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4570"
d="m 200,167.36218 10,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5521"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 a 1,1 0 1 1 -2,0 1,1 0 1 1 2,0 z"
transform="matrix(2,0,0,2,169.78516,52.804161)" />
</g>
</svg>
doc/hdlg/fig/no-sig-detect.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="298.41779"
height="139.18898"
id="svg16149"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="no-sig-detect.svg">
<defs
id="defs16151" />
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="90.634225"
inkscape:cy="40.077438"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="true"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid16157"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
units="mm"
spacingx="0.5mm"
spacingy="0.5mm"
originx="-22.358889mm"
originy="-243.35889mm" />
<sodipodi:guide
orientation="0,1"
position="177.66535,174.12206"
id="guide3808" />
</sodipodi:namedview>
<metadata
id="metadata16154">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-79.224409,-50.877898)">
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 177.16535,122.24407 -44.29133,0 0,-17.71653 -26.57481,0"
id="path16881"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 132.87402,104.52754 141.73228,0"
id="path16883"
inkscape:connector-curvature="0" />
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 274.6063,99.212581 c 0,8.858259 0,8.858259 0,17.716529 12.04146,0 17.71654,-3.5433 17.71654,-8.85827 0,-5.31496 -5.67508,-8.858259 -17.71654,-8.858259 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
inkscape:connector-curvature="0"
id="path5329"
d="m 327.75591,72.63778 0,46.063 14.17323,-7.08662 0,-31.88976 -14.17323,-7.08662"
style="fill:none;stroke:#b2b2b2;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text5331"
y="111.61415"
x="331.29922"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#b2b2b2;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;fill:#b2b2b2;fill-opacity:1"
y="111.61415"
x="331.29922"
id="tspan5333"
sodipodi:role="line">0</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#b2b2b2;fill-opacity:1;stroke:none;font-family:Sans"
x="331.29922"
y="86.81102"
id="text5335"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan5337"
x="331.29922"
y="86.81102"
style="font-size:10px;fill:#b2b2b2;fill-opacity:1">1</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 177.16536,171.85037 -26.57481,0"
id="path4566"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="translate(22.890778,121.24404)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path4618"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.56;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<text
sodipodi:linespacing="125%"
id="text4622"
y="175.39368"
x="148.81889"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="175.39368"
x="148.81889"
sodipodi:role="line"
id="tspan3013"
style="text-align:end;text-anchor:end">20 MHz</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 239.17323,122.24407 17.71653,0 0,-10.62992 17.71654,0"
id="path16971"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 292.32283,108.07084 8.85827,0"
id="path16973"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#b2b2b2;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 186.02362,76.18106 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
id="path3785"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:none;stroke:#b2b2b2;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path3787"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.24999996,0,0,0.24999996,165.9614,54.035404)" />
<path
style="fill:none;stroke:#b2b2b2;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 207.28346,83.267694 120.47245,0"
id="path4053"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#b2b2b2;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 186.02362,83.267694 -106.299211,0"
id="path17002"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path17016"
d="m 377.3622,95.669269 -35.43307,0"
style="fill:none;stroke:#b2b2b2;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:type="arc"
style="fill:#b2b2b2;fill-opacity:1;fill-rule:nonzero;stroke:#b2b2b2;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path17020"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(-12.542293,99.984196)" />
<path
style="fill:none;stroke:#b2b2b2;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 97.440945,83.267694 0,21.259856 8.858265,-1e-5"
id="path17022"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccc" />
<g
id="g3810">
<path
sodipodi:type="arc"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path3020"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(65.410462,154.90546)" />
<rect
y="113.3858"
x="177.16536"
height="70.866119"
width="62.007866"
id="rect16159"
style="opacity:0.98999999;fill:#000000;fill-opacity:0.1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<path
sodipodi:nodetypes="ccc"
inkscape:connector-curvature="0"
id="path4425"
d="m 177.16535,166.53541 7.92662,5.2844 -7.92662,5.34552"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text16885"
y="125.78738"
x="178.93701"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="125.78738"
x="178.93701"
id="tspan16887"
sodipodi:role="line">cnt</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="214.37007"
y="125.78738"
id="text16889"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan16891"
x="214.37007"
y="125.78738">en_o</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="207.28346"
y="157.67714"
id="text3010"
sodipodi:linespacing="125%"><tspan
style="font-size:12px;font-weight:bold;text-align:center;text-anchor:middle"
sodipodi:role="line"
id="tspan3012"
x="207.28346"
y="157.67714">&lt;1999</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="178.93701"
y="141.73225"
id="text3012"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3014"
x="178.93701"
y="141.73225">rst</tspan></text>
</g>
<path
sodipodi:type="arc"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.56;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path3016"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(22.890778,138.96057)" />
<path
style="fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 132.87401,122.24407 0,15.94488 40.74804,0"
id="path3790"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="242.71654"
y="131.10236"
id="text3017"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3019"
x="242.71654"
y="131.10236"
style="font-size:6px">en_o = '1'</tspan><tspan
sodipodi:role="line"
x="242.71654"
y="138.60236"
id="tspan3025"
style="font-size:6px"><tspan
style="font-size:6px;font-weight:bold"
id="tspan3027">if</tspan> cnt &lt; 1999</tspan><tspan
sodipodi:role="line"
x="242.71654"
y="146.10236"
style="font-size:6px"
id="tspan3825">(line high for</tspan><tspan
sodipodi:role="line"
x="242.71654"
y="153.60236"
style="font-size:6px"
id="tspan3827">&lt;100 us)</tspan></text>
<rect
y="95.669281"
x="106.29921"
height="93.897598"
width="194.8819"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:6, 2;stroke-dashoffset:0"
rx="8.858223"
ry="8.858223" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 221.95669,57.192925 26.57481,0"
id="path3036"
inkscape:connector-curvature="0"
transform="translate(79.224409,50.87793)" />
</g>
</svg>
doc/hdlg/fig/ohwr-logo.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with sK1/UniConvertor (http://sk1project.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="595.276pt"
height="841.89pt"
viewBox="0 0 595.276 841.89"
fill-rule="evenodd"
id="svg2"
version="1.1"
inkscape:version="0.47pre4 r22446"
sodipodi:docname="ohr_logo.svg"
inkscape:export-filename="/home/kikito/Desktop/ohr_logo.png"
inkscape:export-xdpi="126.50246"
inkscape:export-ydpi="126.50246">
<metadata
id="metadata280">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<sodipodi:namedview
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1"
objecttolerance="10"
gridtolerance="10"
guidetolerance="10"
inkscape:pageopacity="0"
inkscape:pageshadow="2"
inkscape:window-width="1440"
inkscape:window-height="850"
id="namedview278"
showgrid="false"
inkscape:zoom="0.63429547"
inkscape:cx="154.33516"
inkscape:cy="531.90964"
inkscape:window-x="0"
inkscape:window-y="25"
inkscape:window-maximized="1"
inkscape:current-layer="svg2" />
<defs
id="defs4">
<inkscape:perspective
sodipodi:type="inkscape:persp3d"
inkscape:vp_x="0 : 526.18127 : 1"
inkscape:vp_y="0 : 1000 : 0"
inkscape:vp_z="744.09497 : 526.18127 : 1"
inkscape:persp3d-origin="372.04749 : 350.78752 : 1"
id="perspective282" />
<marker
id="ArrowEnd"
viewBox="0 0 10 10"
refX="0"
refY="5"
markerUnits="strokeWidth"
markerWidth="4"
markerHeight="3"
orient="auto">
<path
d="M 0 0 L 10 5 L 0 10 z"
id="path7" />
</marker>
<marker
id="ArrowStart"
viewBox="0 0 10 10"
refX="10"
refY="5"
markerUnits="strokeWidth"
markerWidth="4"
markerHeight="3"
orient="auto">
<path
d="M 10 0 L 0 5 L 10 10 z"
id="path10" />
</marker>
</defs>
<g
id="g3499"
inkscape:export-xdpi="90"
inkscape:export-ydpi="90">
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 107.755,514.353 c -5.661,-12.668 -2.428,-72.033 27.045,-123.394 22.747,-41.806 31.009,-41.861 72.045,-90.603 8.161,-9.826 9.689,-34.606 8.637,-75.755 -1.802,-55.035 14.078,-78.473 27.341,-89.73 5.865,-4.977 10.547,-7.841 14.105,-9.545 37.228,-21.361 78.903,-14.392 104.265,-5.733 3.859,1.407 7.059,3.561 10.358,5.884 21.543,15.169 31.746,47.617 30.424,75.788 -1.411,33.732 -4.26,62.909 5.092,72.584 34.4,32.294 52.584,62.536 67.218,89.578 3.994,7.378 15.965,32.437 19.234,42.973 5.74,21.891 1.526,58.494 -2.018,74.667 3.554,2.424 9.949,8.448 15.019,12.008 13.194,8.326 33.776,16.462 32.95,23.841 -0.392,5.225 -37.929,59.66 -53.917,85.024 -21.622,32.656 -52.625,70.038 -55.664,72.853 -3.51,3.063 -9.044,4.89 -13.678,5.142 -1.665,0.221 -12.546,-3.138 -25.919,-5.724 -12.175,-2.353 -27.482,-4.546 -37.974,-6.055 -5.657,-1.888 -9.645,-11.663 -13.22,-11.761 -7.337,0.199 -23.69,-3.125 -39.484,1.401 -12.9,1.922 -15.965,1.621 -30.255,0.569 -5.256,-1.29 -5.352,-3.138 -7.073,-1.194 -6.908,11.395 -15.781,25.698 -31.42,35.82 -0.768,0.734 -4.275,-0.045 -5.75,-0.609 -35.648,-13.625 -41.715,-6.383 -98.64,-30.944 -14.633,-5.781 -37.7825,-15.278 -49.3237,-18.371 -2.6059,-0.699 -4.0742,-3.158 -5.1835,-3.826 -1.5764,-0.893 -4.3026,-1.048 -5.8114,-1.619 -14.5759,-5.507 -16.3689,-17.271 -15.4357,-19.91 2.4742,-11.348 4.645,-17.421 8.1421,-26.956 11.29,-31.507 26.0679,-51.947 41.5342,-73.392 0.821,-2.451 8.543,-1.378 7.357,-3.011 z"
id="path18" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 225.082,191.519 c 0.121,-1.355 1.131,-3.089 1.944,-2.949 15.396,2.651 26.629,0.066 59.797,-3.31 2.052,-0.409 2.566,1.596 2.759,2.472 2.918,13.25 3.328,24.422 6.093,39.511 0.856,4.578 0.139,5.131 -2.364,6.529 -32.127,9.828 -43.471,22.124 -62.592,33.738 -1.62,0.985 -5.331,3.049 -4.775,-0.453 -1.669,-26.851 -3.398,-48.647 -0.862,-75.538 z"
id="path20" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 333.076,304.867 c 9.991,-7.049 16.336,-13.305 27.018,-18.674 2.198,-1.059 7.122,-10.116 4.789,-12.047 -1.975,-2.075 -2.534,-3.341 -1.611,-8.126 0.243,-3.622 0.569,-6.371 -1.059,-9.728 -0.327,-0.456 -1.283,-3.711 -6.181,-1.053 -0.559,0.664 -1.314,0.462 -2.03,0.062 -14.772,-7.373 -30.275,-18.78 -48.385,-21.397 -1.872,-0.464 -2.519,-2.224 -3.073,-5.382 -3.054,-17.195 -2.474,-31.38 -4.845,-48.302 -0.559,-1.931 -4.503,-5.359 -8.967,-3.97 -8.342,3.599 -33.849,7.498 -59.109,6.906 -1.951,-0.482 -4.344,0.319 -3.668,-3.667 4.56,-19.272 3.716,-21.915 23.916,-41.891 38.35,-31.721 111.302,-22.676 122.21,28.926 4.099,17.731 6.568,60.64 -0.597,95.909 -0.535,4.698 -0.96,9.285 1.697,13.51 14.242,20.576 31.349,34.56 49.562,50.885 13.271,10.635 46.231,49.613 53.953,91.5 2.585,14.518 4.455,30.965 1.328,50.454 -0.132,0.397 -0.205,1.137 -2.053,0.154 -11.715,-8.161 -24.455,-10.028 -33.638,-10.147 -3.193,-0.041 -3.118,-1.618 -3.069,-2.293 0.19,-8.567 0.634,-17.304 -0.71,-26.727 -1.472,-10.045 -7.148,-28.792 -22.716,-46.376 -2.106,-2.485 -5.204,-5.277 -11.335,-3.988 -3.5,0.875 -4.048,3.815 -3.399,6.44 4.357,15.671 12.446,28.859 13.381,51.226 -7.064,-11.201 -18.334,-24.119 -27.112,-34.54 -17.041,-17.015 -16.463,-18.441 -34.309,-28.444 -3.039,-1.305 -6.802,-2.296 -9.149,-3.601 -3.123,-1.595 -2.713,-5.43 -3.268,-8.007 -2.854,-18.884 -5.307,-33.003 -8.291,-52.254 -0.307,-1.31 -1.162,-4.158 0.72,-5.358 z"
id="path22" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 67.4257,623.695 c 14.0267,-54.464 33.2903,-66.747 53.8463,-100.062 3.215,-4.014 1.522,-3.582 -2.511,-2.086 -5.854,2.173 -6.889,-1.95 -14.409,4.888 -7.4603,6.783 -15.8039,22.053 -19.9727,28.661 -9.7038,17.012 -14.6677,27.543 -20.0041,41.488 -6.9562,16.113 -9.1531,29.193 0.1743,31.341 1.5424,0.356 1.6372,1.249 2.8762,-4.23 z"
id="path24" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 223.509,595.27 c -13.932,-13.931 -32.698,-29.305 -47.886,-42.114 -8.165,-6.888 -21.045,-17.267 -27.499,-21.995 -18.706,-13.703 -21.209,-2.344 -30.422,10.561 l -11.92,16.696 c -7.6585,10.727 -22.7348,34.92 -25.9552,48.128 -2.3658,9.701 -10.6312,22.228 1.2886,28.027 9.4062,7.588 84.6446,34.736 106.6496,39.513 11.865,2.575 18.951,3.877 32.241,5.558 17.233,2.178 35.505,-26.493 42.145,-40.268 2.876,-5.965 -13.753,-15.829 -19.215,-23.306 -4.071,-5.574 -10.48,-10.882 -19.427,-20.8 z"
id="path26" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 91.5647,634.558 c -5.6582,-1.042 -8.1074,-3.19 -5.071,-8.372 3.0365,-5.181 6.9497,-13.176 13.1321,-26.58 0.9912,-2.15 2.4962,-4.954 8.1122,-1.001 5.264,3.705 14.206,11.15 23.836,18.209 0.641,0.47 3.066,2.718 -0.2,5.912 -4.087,7.218 -3.667,9.693 -6.093,17.386 -0.826,2.608 -2.897,4.115 -7.694,1.658 -4.798,-2.458 -20.3641,-6.171 -26.0223,-7.212 z"
id="path28" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 98.4522,629.527 c -3.6944,-0.655 -5.2936,-2.007 -3.3111,-5.268 1.9826,-3.261 4.5377,-8.293 8.5749,-16.728 0.647,-1.353 1.629,-3.118 5.296,-0.63 3.437,2.332 9.276,7.017 15.563,11.459 0.419,0.296 2.002,1.711 -0.13,3.721 -2.669,4.543 -2.394,6.1 -3.978,10.942 -0.539,1.641 -1.892,2.589 -5.024,1.043 -3.133,-1.547 -13.296,-3.884 -16.9908,-4.539 z"
id="path30" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 118.049,512.132 c -6.71,-7.445 -4.264,-29.25 -1.675,-47.94 20.578,-86.046 46.603,-106.942 95.483,-155.85 3.43,-3.144 6.805,-7.069 8.245,-11.954 1.776,-7.094 3.648,-20.767 5.968,-20.269 1.864,0 0.258,-0.325 2.883,0.109 2.603,0.286 -0.65,10.661 1.519,12.574 13.994,16.271 21.91,15.299 21.877,20.208 0.408,3.182 1.738,5.733 2.239,8.476 3.564,19.524 5.688,27.751 4.23,52.557 -0.602,5.044 -2.255,4.757 -3.664,5.796 -58.282,33.955 -68.512,78.379 -73.274,111.967 -8.011,-20.073 -6.951,-48.693 4.648,-86.257 0.338,-1.404 1.468,-3.073 2.506,-4.626 4.041,-5.663 -5.011,-12.076 -9.578,-5.663 -22.607,30.029 -29.279,61.28 -26.173,89.267 5.306,26.262 25.034,47.115 45.364,63.161 22.097,18.25 22.908,20.754 32.341,31.399 3.523,5.861 -5.768,13.103 -8.58,9.324 -29.863,-26.796 -56.24,-50.309 -88.084,-71.842 -1.026,-0.694 -2.06,-1.566 -3.989,-1.601 -4.273,0.745 -11.574,2.68 -12.286,1.164 z"
id="path32" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 294.009,327.753 c -1.609,18.521 -0.105,37.527 0.784,56.518 -12.151,2.445 -17.594,3.373 -27.457,7.085 -29.188,11.01 -40.509,24.793 -58.915,57.059 -10.405,25.766 -9,47.682 -11.124,83.234 -16.858,-11.595 -31.971,-34.75 -34.987,-48.805 -6.692,-29.607 6.75,-60.493 13.951,-74.531 -10.621,45.371 -9.071,64.266 0.711,88.674 2.647,4.413 8.193,8.083 11.997,5.919 2.893,-2.325 1.066,-11.209 1.786,-16.433 2.259,-45.762 29.602,-87.782 71.207,-103.815 6.742,-2.585 5.147,-1.917 5.374,-6.61 0.149,-18.388 0.127,-38.509 -5.155,-59.272 -3.027,-8.71 3.938,-3.501 7.573,-1.505 7.889,4.217 16.366,9.336 24.255,12.482 z"
id="path34" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 281.418,342.075 c -0.264,0.183 -0.527,0.365 -0.785,0.549 2.375,0.039 4.638,0.587 6.344,2.638 3.824,4.6 1.742,13.093 -5.134,12.885 -6.152,-0.186 -10.642,-6.552 -8.384,-12.419 0.747,-1.941 2.36,-3.768 4.483,-4.207 1.184,-0.245 2.313,0.223 3.476,0.554 z"
id="path36" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 281.559,362.52 c -0.226,0.669 -0.476,1.329 -0.724,1.987 3.878,1.176 7.422,3.962 6.477,8.55 -1.155,5.613 -11.374,8.345 -12.671,1.49 -0.648,-3.425 0.41,-7.248 2.744,-9.682 -0.192,-0.154 -0.368,-0.298 -0.52,-0.432 l 0.114,-0.572 c 0.452,0.014 0.92,0.052 1.397,0.115 0.921,-0.704 1.988,-1.214 3.183,-1.456 z"
id="path38" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 273.868,321.819 0.141,-0.368 c 3.157,-0.576 6.555,-0.64 8.874,2.055 3.738,4.345 0.107,13.443 -6.128,11.501 -3.959,-1.234 -8.424,-6.332 -6.277,-10.661 0.81,-1.631 1.995,-2.285 3.39,-2.527 z"
id="path40" />
<path
style="fill:none;stroke:#ff0000;stroke-width:0.500094"
d="m 278.38,329.04 0.026,-0.005 0.013,-0.013 0.006,-0.01 -0.045,0.028 z"
id="path42" />
<path
style="fill:#767b82;stroke:#676f79;stroke-width:0.500094"
d="m 300.096,326.255 c -0.385,12.457 -0.139,31.878 0.96,38.269 0.427,10.884 0.924,14.981 0.816,18.582 23.806,-3.953 38.885,-1.19 48.696,4.928 16.884,12.628 26.771,23.593 35.84,36.456 4.21,5.795 13.99,28.362 12.441,39.189 8.105,-3.923 19.249,-5.798 30.426,-5.624 1.062,-5.425 7.014,-35.772 -15.674,-64.863 4.968,17.92 10.255,38.332 8.207,57.236 -1.459,4.571 -8.977,5.332 -10.679,1.368 -3.449,-13.224 -2.686,-12.062 -8.768,-20.253 -13.258,-17.709 -24.737,-32.038 -41.375,-44.589 -5.815,-4.631 -7.212,-6.602 -21.212,-11.028 -2.009,-1.067 -9.561,-0.335 -7.148,-8.174 2.079,-7.055 -4.121,-33.797 -6.799,-52.945 -0.077,-7.553 -7.015,-0.787 -8.086,-0.386 -7.15,5.028 -17.499,11.106 -17.645,11.834 z"
id="path44" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 368.464,479.697 c 1.592,3.184 6.129,4.788 9.693,5.893 1.866,0.579 4.908,-2.632 8.083,-2.58 3.487,0.057 1.86,-1.873 1.86,-4.87 0,-4.776 -3.728,-3.602 -7.918,-2.884 l -7.159,1.227 c -1.383,0.236 -5.683,1.528 -4.559,3.214 z"
id="path46" />
<path
style="fill:#417c29;stroke:#417c29;stroke-width:0.500094"
d="m 233.268,460.889 c 20.193,-0.267 68.437,-8.591 82.849,-8.965 l 23.804,-0.618 c 6.799,-0.177 16.016,-0.52 29.678,3.4 1.327,0.381 2.183,0.306 2.473,1.855 1.564,8.343 0.23,13.092 -3.401,13.911 -10.305,2.327 -10.548,11.712 -13.911,25.968 -4.472,18.958 -4.935,26.751 -6.214,30.63 -0.337,1.022 -5.611,-1.284 -17.576,2.166 -16.6,2.013 -43.935,2.959 -45.998,3.048 -42.753,1.845 -55.842,5.006 -55.842,-15.706 0,-8.795 -3.022,-55.689 4.138,-55.689 z"
id="path48" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 107.344,580.938 18.791,-35.711 c 2.997,-5.696 7.418,-11.506 14.976,-5.336 3.8,3.102 8.675,7.332 11.853,8.524 6.254,2.346 9.091,6.789 5.388,10.709 -3.077,3.256 -7.076,11.3 -9.635,17.561 -1.957,4.787 -4.355,10.724 -6.101,16.553 -5.061,16.899 -6.809,18.705 -17.285,10.333 l -4.943,-3.949 c -5.047,-4.034 -11.9,-11.919 -13.597,-13.423 -2.134,-1.891 0.981,-4.808 0.553,-5.261 z"
id="path50" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 113.135,583.573 c 2.546,3.587 7.105,8.127 10.807,10.555 3.354,2.199 5.306,4.736 9.359,5.018 0.923,0.064 1.736,-2.695 2.486,-4.534 1.091,-2.672 3.105,-11.359 3.439,-12.418 2.1,-6.664 14.43,-25.125 10.274,-28.981 -1.919,-1.781 -5.207,-3.24 -6.942,-4.976 -4.05,-4.049 -8.93,-5.791 -10.992,0.463 -1.175,3.565 -10.451,19.726 -12.959,23.488 -1.762,2.643 -5.588,8.261 -5.472,11.385 z"
id="path52" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 337.347,637.313 c -10.749,4.217 -38.481,12.749 -65.238,3.463 -10.196,11.363 1.019,10.633 12.465,9.824 10.074,-0.713 19.593,-1.061 29.914,-2.506 6.053,-0.847 14.506,0.547 20.672,0.7 4.372,0.107 3.129,-2.12 2.395,-5.504 -0.433,-1.992 -0.387,-3.984 -0.208,-5.977 z"
id="path54" />
<path
style="fill:#b6bcc6;stroke:#b6bcc6;stroke-width:0.500094"
d="m 239.955,568.996 c 2.23,8.911 -0.22,18.478 -4.334,21.548 -3.845,2.717 -2.712,3.582 -1.082,5.289 16.895,17.56 22.452,22.72 36.889,34.886 15.87,10.488 46.415,8.17 64.008,-2.299 1.45,-0.767 2.848,-2.747 2.793,-4.736 -0.633,-22.764 1.465,-55.995 8.341,-84.538 0.776,-3.397 -2.277,-3.083 -2.772,-3.108 -31.698,1.954 -55.738,4.741 -77.736,4.323 -14.084,-0.799 -37.714,3.891 -42.043,-1.983 -6.963,-10.44 -1.362,-26.19 -2.249,-38.7 -1.064,-15.025 -1.458,-36.783 3.14,-42.175 7.005,-8.217 46.451,-5.78 74.215,-11.397 31.608,-3.773 49.453,-3.142 68.912,-1.608 2.865,0.323 11.658,4.022 11.323,8.98 -0.201,4.026 -1.242,8.144 -0.23,12.729 0.804,2.953 1.61,2.361 3.534,2.608 3.334,-0.143 2.737,0.106 4.71,-0.201 2.624,-0.666 0.942,-1.432 1.291,-5.375 0.229,-14.171 -4.722,-33.729 -26.016,-54.322 -21.293,-20.592 -30.799,-20.643 -51.81,-20.334 -38.953,4.217 -60.911,15.299 -76.078,32 -20.909,27.808 -32.34,47.744 -30.032,111.02 0.163,7.889 4.383,12.397 24.472,24.345 l 10.754,13.048 z"
id="path56" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 355.62,529.278 c 0.549,-3.005 6.013,-31.122 7.105,-35.477 1.371,-5.465 1.828,-6.428 6.176,-5.192 8.566,2.438 4.819,13.435 4.049,21.132 -1.292,12.917 -2.427,24.425 -3.914,36.21 -2.907,23.042 -7.973,50.453 -13.074,74.879 -2.228,10.67 -2.534,25.814 -5.521,33.163 -0.418,1.03 -3.024,-0.418 -3.495,-2.898 -4.087,-21.524 -1.217,-34.093 -1.217,-55.593 0,-14.063 7.259,-51.817 9.891,-66.224 z"
id="path58" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 359.828,651.35 c 6.968,-42.449 16.399,-97.964 23.748,-149.613 0.306,-1.943 4.034,-6.907 5.481,-7.48 5.44,-2.914 6.286,-4.589 11.726,-7.503 25.645,1.36 54.178,4.295 79.823,5.655 16.734,5.949 29.794,11.505 40.097,19.029 4.867,2.915 6.504,12.219 2.405,17.895 -8.018,13.159 -17.424,25.551 -25.592,38.584 -19.932,31.8 -39.627,61.582 -65.259,90.194 -3.692,4.604 -11.017,13.695 -20.692,11.889 -13.677,-4.332 -28.85,-5.673 -41.673,-7.227 -7.557,-0.602 -11.054,-7.188 -10.064,-11.423 z"
id="path60" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 482.131,528.976 c -1.24,2.617 -3.135,5.104 -5.427,8.592 -1.732,2.636 -3.56,8.568 0.613,10.55 l 9.027,4.287 c 2.513,1.193 2.638,3.744 3.605,3.714 7.3,-0.23 1.515,-0.835 10.207,-7.899 1.874,-1.522 4.365,-4.669 5.873,-6.478 l 7.763,-9.313 c 8.035,-4.775 3.367,-9.623 -2.964,-12.71 -4.453,-2.172 -12.663,-5.425 -17.849,-5.425 -1.051,0 -3.537,0.906 -4.076,1.679 -2.11,3.025 -4.736,8.702 -6.772,13.003 z"
id="path62" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 392.849,500.413 75.864,3.525 c 3.249,0.151 8.808,1.341 12.127,1.974 2.804,0.536 5.621,2.533 4.794,5.218 -0.786,2.554 -11.571,16.516 -11.986,17.062 -1.95,2.567 -9.215,16.357 -14.101,16.357 -9.165,0 -20.165,-3.95 -29.753,-5.499 -9.622,-1.554 -20.341,-3.103 -30.036,-4.089 -10.1,-1.029 -12.991,-2.183 -11.844,-11.845 0.987,-8.32 -0.706,-20.87 4.935,-22.703 z"
id="path64" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 250.062,205.816 c 0.002,0 0.004,-0.001 0.006,-0.002 0.096,-0.035 0.194,-0.065 0.292,-0.091 5.797,-1.844 11.86,-4.389 18.071,-3.058 5.138,1.101 10.974,5.938 13.68,10.413 3.165,5.232 1.541,11.415 -1.495,16.3 -6.549,10.538 -20.003,18.998 -32.287,14.085 -5.353,-2.141 -10.193,-5.673 -11.845,-11.478 -1.648,-5.789 -0.555,-12.401 3.196,-17.132 l 9.062,-8.196 c 0.006,-0.007 0.014,-0.013 0.021,-0.02 0.119,-0.117 0.246,-0.226 0.382,-0.327 0.011,-0.008 0.023,-0.017 0.034,-0.025 0.019,-0.014 0.037,-0.027 0.056,-0.04 0.006,-0.004 0.011,-0.008 0.017,-0.011 0.045,-0.031 0.089,-0.061 0.135,-0.089 0.012,-0.008 0.025,-0.015 0.038,-0.023 0.197,-0.12 0.405,-0.22 0.618,-0.299 0.006,-0.002 0.012,-0.005 0.019,-0.007 z"
id="path66" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 300.245,315.651 c 1.574,0.947 2.515,-0.606 10.498,-5.352 7.187,-4.273 15.25,-7.945 20.533,-11.763 7.354,-5.315 25.549,-17.509 24.641,-25.042 -0.642,-5.321 -14.214,10.566 -18.936,14.215 -10.67,8.247 -20.691,18.004 -35.328,24.669 -1.166,0.576 -2.139,2.442 -1.408,3.273 z"
id="path68" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 238.507,279.676 c 1.909,0.597 6.445,4.889 7.159,5.369 l 6.204,4.176 c 2.387,1.552 8.966,4.859 11.693,6.205 6.46,3.188 14.731,8.157 20.762,12.409 l 9.306,6.562 c 4.417,3.114 -5.012,3.361 -11.096,-0.477 -4.609,-2.907 -13.006,-5.803 -18.733,-9.187 -4.88,-2.884 -14.437,-7.159 -18.494,-10.858 -2.563,-2.337 -5.748,-3.694 -6.682,-7.517 -0.378,-1.546 -2.148,-7.04 -0.119,-6.682 z"
id="path70" />
<path
style="fill:#f8d222;stroke:#f8d222;stroke-width:0.500094"
d="m 244.212,274.334 c 0.191,2.278 5.742,6.266 8.352,7.403 7.403,3.227 15.172,8.003 20.501,10.63 8.148,4.016 13.668,11.39 24.108,11.39 5.505,0 14.502,-7.123 18.982,-10.061 6.075,-3.983 12.067,-8.629 17.084,-13.288 l 15.945,-14.806 c 2.837,-2.634 -1.374,-4.982 -4.745,-7.593 -6.409,-4.963 -10.058,-4.947 -18.983,-10.06 -7.083,-4.059 -19.843,-7.971 -28.473,-6.644 -7.403,1.138 -18.638,6.738 -26.006,10.44 -8.674,4.358 -26.955,14.047 -26.765,22.589 z"
id="path72" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 297.904,545.735 c 2.396,-0.288 4.556,0.259 5.919,2.701 2.06,3.686 -0.232,7.974 -4.483,7.802 -3.554,-0.144 -8.933,-3.863 -6.925,-8.003 1.011,-2.084 3.189,-2.289 5.237,-2.515 0.086,0 0.169,0.005 0.252,0.015 z"
id="path74" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 294.603,560.095 c 0.438,-0.516 1.128,-0.794 1.843,-0.675 3.294,1.113 6.066,4.692 4.64,8.272 -1.198,3.005 -5.618,1.937 -7.535,0.531 -2.1,-1.54 -3.415,-4.711 -1.413,-6.86 0.701,-0.753 1.55,-1.086 2.465,-1.268 z"
id="path76" />
<path
style="fill:none;stroke:none"
d="m 295.859,248.272 -3.157,21.914 c -1.485,10.309 1.044,10.501 1.26,22.27"
id="path80" />
<path
style="fill:#1f2123;stroke:#1f2123;stroke-width:0.500094"
d="m 467.032,370.467 c -19.85,-45.516 -51.177,-74.955 -60.487,-85.241 -0.147,-0.163 -0.29,-0.322 -0.426,-0.475 -5.555,-6.336 -12.057,-13.893 -13.059,-25.558 0.993,-23.854 2.247,-42.934 0.369,-65.301 -1.801,-28.672 -6.944,-59.21 -43.6,-69.757 30.16,20.427 29.66,42.071 32.427,61.447 1.985,24.27 -1.256,56.069 -1.545,71.746 -1.87,20.407 10.016,26.761 14.744,32.878 13.685,14.682 50.186,44.053 71.577,80.261 z"
id="path82" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 464.018,508.461 c 1.79,0 13.877,1.413 10.307,7.147 -4.252,6.826 -4.648,9.844 -9.88,16.65 -7.507,9.764 -13.314,5.362 -19.591,4.304 l -23.768,-4.002 c -27.075,-4.561 -25.359,-3.802 -25.359,-8.88 l 0,-12.528 c 17.301,-3.191 36.202,1.265 53.259,-2.884 1.998,-0.461 10.603,-2.459 12.14,-0.922 0.614,0.614 2.485,0.962 2.892,1.115 z"
id="path84" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 310.591,548.58 c 0.421,-1.593 1.319,-2.973 3.257,-3.183 3.292,-0.356 9.214,2.81 8.056,6.832 -0.826,2.867 -5.66,4.193 -8.116,2.885 -1.5,-0.8 -2.313,-2.316 -3.28,-3.642 -0.776,-0.777 -0.776,-2.036 0,-2.812 0.028,-0.028 0.055,-0.054 0.083,-0.08 z"
id="path86" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 314.978,559.301 c 1.714,2.222 2.526,5.314 1.347,7.969 -1.123,2.526 -3.846,2.472 -5.775,0.918 -2.448,-1.972 -3.504,-5.559 -1.937,-8.409 0.902,-1.639 2.286,-2.359 3.948,-3.025 1.059,-0.293 2.155,0.327 2.448,1.385 0.111,0.397 0.091,0.799 -0.031,1.162 z"
id="path88" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 296.969,549.787 -0.762,0.101 -0.149,0.064 -0.024,0.014 0.015,0.074 0.118,0.279 c 0.528,0.909 4.496,3.388 4.448,1.075 -0.034,-1.639 -1.255,-2.032 -2.614,-1.707 -0.341,0.129 -0.696,0.157 -1.032,0.1 z"
id="path90" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 296.355,563.842 -1.091,0.136 -0.125,0.049 -0.014,0.007 0.005,0.026 0.082,0.191 c 0.485,0.837 1.345,1.21 2.253,1.363 l -0.064,-0.264 c -0.22,-0.528 -0.484,-1.097 -0.887,-1.516 -0.052,0.005 -0.105,0.008 -0.159,0.008 z"
id="path92" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 325.735,547.45 c 2.512,-3.106 8.664,-3.632 10.675,0.448 1.113,2.258 0.132,5.033 -2.494,5.421 -1.802,0.266 -3.656,-0.584 -5.293,-1.182 l -0.453,-0.175 -0.077,-0.028 c -1.058,-0.045 -1.901,-0.916 -1.901,-1.986 0,-0.004 10e-4,-0.007 10e-4,-0.01 -0.715,-0.6 -0.929,-1.641 -0.458,-2.488 z"
id="path94" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 330.829,558.627 c 2.469,1.107 6.172,2.711 5.033,5.892 -1.471,4.106 -8.986,4.958 -10.499,0.49 -0.97,-2.866 0.848,-5.174 3.004,-6.765 0.824,-0.475 1.847,-0.293 2.462,0.383 z"
id="path96" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 270.164,546.402 c 4.619,-1.875 11.107,-0.078 13.616,4.334 3.166,5.567 4.467,12.057 -1.42,16.231 -5.239,3.714 -14.483,3.822 -18.817,-1.429 -4.008,-4.856 -3.843,-12.723 1.146,-16.827 1.685,-1.386 3.495,-1.985 5.475,-2.309 z"
id="path98" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 267.302,556.065 c -0.123,0.483 -0.16,1.019 -0.089,1.608 0.684,5.661 7.078,6.884 11.448,3.938 3.969,-2.675 -0.421,-9.713 -4.77,-9.419 -0.035,0.021 -0.07,0.042 -0.106,0.061 1.06,0.754 1.606,2.106 1.271,3.444 -0.436,1.744 -2.202,2.804 -3.946,2.368 -1.231,-0.445 -2.677,-1.094 -3.808,-2 z"
id="path100" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 314.265,550.164 c 0.558,0.884 1.21,1.628 2.302,1.336 l 1.17,-0.385 -0.125,-0.195 -0.777,-0.741 -0.912,-0.556 c -1.298,-0.666 -1.573,-0.493 -1.658,0.541 z"
id="path102" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 312.107,561.91 c -0.448,0.921 -0.245,2.067 0.686,2.959 l 0.006,-0.231 c -0.09,-0.906 -0.214,-1.927 -0.692,-2.728 z"
id="path104" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 331.605,548.968 c 0.264,0.096 0.51,0.183 0.73,0.246 l 0.268,0.06 c -0.226,-0.183 -0.588,-0.276 -0.998,-0.306 z"
id="path106" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 329.538,562.469 c -0.456,0.535 -0.812,1.194 -0.249,1.513 0.617,0.35 1.63,-0.199 2.201,-0.501 l -1.952,-1.012 z"
id="path108" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 253.347,563.463 c -0.005,0.891 -0.374,1.778 -1.093,2.417 -4.581,3.154 -9.342,5.848 -15.118,4.294 -8.297,-2.233 -12.905,-12.736 -8.108,-20.108 4.297,-6.603 12.28,-5.68 18.964,-4.055 6.926,1.685 6.809,9.464 6.065,15.006 -0.111,0.827 -0.347,1.671 -0.71,2.446 z"
id="path110" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 245.615,557.205 1.955,1.829 0.173,0.129 c 0.369,-2.508 1.144,-6.356 -2.013,-7.049 -4.155,-0.912 -10.961,-2.255 -12.048,3.552 -0.648,3.462 1.699,7.306 5.124,8.218 1.523,0.405 2.936,0.267 4.272,-0.171 -0.713,-0.645 -1.394,-1.312 -2.065,-1.906 -1.271,-1.271 -1.271,-3.331 0,-4.602 1.271,-1.27 3.331,-1.27 4.602,0 z"
id="path112" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 248.165,498.513 9.59,-5.826 c 5.089,-2.321 10.436,-1.122 15.858,-1.833 5.609,-0.735 12.658,-3.012 13.985,-9.454 0.905,-4.396 1.957,-10.386 -0.558,-14.532 -4.122,-6.792 -14.222,-5.811 -20.805,-5.094 -8.498,0.925 -17.133,4.004 -23.302,10.112 -4.848,4.802 -6.515,10.098 -8.147,16.164 -1.436,4.793 -0.679,10.423 4.714,12.833 3.608,1.613 6.177,-0.82 8.665,-2.37 z"
id="path114" />
<path
style="fill:#adeca8;stroke:#adeca8;stroke-width:0.500094"
d="m 243.091,493.939 c -2.522,1.479 -1.809,-3.165 -1.428,-4.431 1.467,-5.428 2.725,-9.551 6.491,-13.262 7.051,-6.946 17.425,-8.622 26.914,-8.729 1.566,-0.018 6.883,0.236 7.2,2.857 0.376,3.109 1.222,9.121 -1.906,11.536 -4.483,3.463 -11.499,2.193 -16.693,2.52 -6.009,0.377 -16.307,5.274 -20.578,9.509 z"
id="path116" />
<path
style="fill:#d2f799;stroke:#d2f799;stroke-width:0.500094"
d="m 354.161,499.012 c -0.272,1.187 -0.527,2.326 -0.768,3.421 -0.338,0.189 -0.727,0.297 -1.143,0.297 -4.945,0.382 -11.024,2.019 -16,0.841 -4.57,-1.082 -11.365,-1.696 -15.436,1.133 -2.722,1.891 -5.949,2.138 -7.052,-1.628 l -0.302,-1.363 -0.251,-0.916 -0.048,-0.099 -0.203,-0.012 -0.281,0.021 c -3.75,0.506 -4.53,8.779 -9.192,7.069 -1.632,-0.599 -2.74,-2.446 -3.184,-4.04 l -2.815,-13.974 -2.945,7.099 -5.55,13.378 -0.123,0.27 c -0.657,1.512 -2.907,2.17 -4.084,0.831 -2.1,-2.391 -1.432,-6.373 -3.136,-9.1 -0.732,-1.172 -1.882,-0.377 -2.554,0.552 -2.409,3.338 -2.384,10.958 -8.461,9.154 -3.411,-1.013 -5.846,-4.166 -8.86,-5.908 -1.083,-0.626 -2.643,0.76 -3.517,1.042 -1.625,0.524 -3.309,0.828 -5.013,0.927 l -24.278,1.003 c -0.013,0.001 -0.025,0.001 -0.038,0.001 -0.048,-1.448 -0.101,-3.025 -0.153,-4.697 l 24.469,-1.007 c 3.394,-0.178 6.875,-3.345 10.27,-1.635 3.025,1.522 5.209,4.17 8.199,5.667 l 0.3,0.114 0.073,0.017 0.066,-0.092 0.271,-0.546 0.649,-1.846 c 1.467,-4.016 4.782,-10.124 10.106,-7.549 2.026,0.98 3.155,3.19 3.842,5.287 l 3.18,-7.664 5.549,-13.374 0.195,-0.393 c 0.834,-1.772 3.416,-1.502 4.306,0.008 0.84,1.425 1.067,3.552 1.349,5.074 l 1.847,10.588 1.244,5.087 0.044,0.1 c 2.301,-3.184 5.273,-7.203 9.794,-5.979 1.446,0.391 2.517,1.517 3.053,2.898 l 0.474,1.651 0.034,0.156 c 2.411,-1.603 4.47,-2.192 7.402,-2.454 l 2.697,-0.205 5.26,-0.01 4.167,0.903 -0.189,-0.091 0.262,0.043 0.549,0.036 0.749,0.003 13.265,-1.071 c 0.788,0 1.485,0.386 1.911,0.982 z"
id="path118" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 278.606,344.29 c -1.223,1.27 -1.84,2.793 -0.933,5.004 0.926,2.258 2.897,2.929 5.159,2.419 1.802,-0.407 1.022,-3.574 0.275,-4.557 -1.003,-1.318 -2.834,-2.127 -4.501,-2.866 z"
id="path120" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 275.57,323.019 c -1.01,1.039 -2.043,2.361 -1.315,3.471 0.678,1.033 1.636,1.807 2.78,2.284 l 0.666,0.221 0.525,0.075 0.154,-0.03 -0.015,0.009 -0.166,0.107 -0.186,0.165 0.129,-0.02 0.264,-0.266 0.073,-0.014 -0.015,-0.033 -0.039,0.024 0.297,-0.475 c 1.486,-2.902 -0.87,-4.241 -3.152,-5.518 z"
id="path122" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 279.961,366.995 c -0.52,1.717 -0.801,3.474 -0.377,5.381 l 0.215,0.479 0.098,0.115 0.068,0.028 0.018,-0.048 -0.044,-0.096 -0.093,-0.107 c -0.575,-0.601 2.303,-0.597 2.453,-1.441 0.268,-1.507 -0.934,-3.019 -2.338,-4.311 z"
id="path124" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 388.055,491.931 c 7.415,11.614 8.662,20.574 14.84,31.834 10.514,16.263 28.007,11.836 31.437,10.404 11.73,-5.163 20.5,-17.082 36.88,-28.388 7.006,-6.081 10.829,-15.698 8.995,-19.834 l -83.308,0.82 -8.844,5.164 z"
id="path126" />
<path
style="fill:#424a53;stroke:#424a53;stroke-width:0.500094"
d="m 413.013,523.761 c -1.306,-0.979 -5.262,-8.427 -6.448,-11.599 -2.689,-7.194 -9.113,-16.83 -9.113,-24.883 0,-8.272 -3.863,-12.212 7.597,-16.81 12.486,-5.009 26.287,-6.181 40.838,-4.396 8.287,1.016 20.914,4.329 25.404,10.903 3.275,4.795 -1.478,18.075 -4.536,20.911 l -17.767,16.482 c -3.862,3.582 -12.447,11.546 -19.63,11.546 -2.612,0 -10.924,1.2 -16.345,-2.154 z"
id="path128" />
<path
style="fill:#efa417;stroke:#efa417;stroke-width:0.500094"
d="m 497.371,520.641 c -4.763,0.772 -11.951,14.588 -14.838,19.526 -3.306,5.657 8.621,8.418 10.232,7.836 4.678,-1.689 7.925,-7.893 8.963,-9.035 2.214,-2.431 10.48,-11.767 7.515,-13.185 -5.084,-2.431 -6.622,-4.793 -11.872,-5.142 z"
id="path130" />
<path
style="fill:none;stroke:none"
d="m 253.108,272.087 c 5.49,-0.845 -0.845,5.912 -0.845,0.422"
id="path134" />
<path
style="fill:none;stroke:none"
d="m 264.51,280.111 c 1.267,-1.056 3.59,-2.956 3.167,0.211 -0.422,2.956 -4.223,-0.634 -2.322,-1.478"
id="path138" />
<path
style="fill:none;stroke:none"
d="m 276.757,287.923 c 0,-8.235 1.056,4.857 0,0.423 -0.422,-1.689 -4.434,1.056 -0.845,-3.168"
id="path142" />
<path
style="fill:none;stroke:none"
d="m 302.307,291.302 c -0.845,-2.745 3.8,-1.689 5.067,-0.422 1.69,1.689 -1.478,4.012 -3.378,1.478"
id="path146" />
<path
style="fill:none;stroke:none"
d="m 318.777,282.645 c 0,-1.69 2.534,-4.012 4.223,-2.534 1.478,1.267 -3.167,3.589 -3.167,1.689"
id="path150" />
<path
style="fill:none;stroke:none"
d="m 338.414,269.342 c -7.39,-2.323 6.546,0.844 -0.211,0.844"
id="path154" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 258.581,132.113 0.295,-1.44 0.068,-0.213 c 0.13,-1.175 1.126,-2.09 2.335,-2.09 1.298,0 2.351,1.053 2.351,2.351 l -0.295,1.44 -0.067,0.209 c -0.128,1.178 -1.126,2.094 -2.337,2.094 -1.298,0 -2.35,-1.053 -2.35,-2.351 z"
id="path156" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 248.739,141.528 c -1.601,-1.055 -3.019,-2.672 -1.344,-4.398 0.638,-0.657 1.543,-0.682 2.394,-0.751 1.298,0 2.35,1.052 2.35,2.35 0,0.118 -0.008,0.235 -0.025,0.348 0.07,0.462 0.002,0.949 -0.222,1.398 -0.58,1.162 -1.992,1.633 -3.153,1.053 z"
id="path158" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 273.344,131.02 c -1.546,-0.923 -4.112,-2.434 -2.777,-4.654 0.924,-1.537 2.721,-1.426 4.292,-1.478 1.298,0 2.35,1.053 2.35,2.351 0,0.479 -0.143,0.926 -0.39,1.297 0.103,0.533 0.022,1.102 -0.268,1.61 -0.644,1.127 -2.08,1.518 -3.207,0.874 z"
id="path160" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 284.175,129.549 c -2.051,-0.676 -4.142,-1.562 -3.837,-4.14 0.318,-2.692 4.103,-4.802 6.369,-3.022 1.622,1.274 0.924,3.253 0.351,4.858 -0.033,0.067 -0.069,0.132 -0.107,0.194 -0.007,0.077 -0.018,0.154 -0.033,0.232 -0.239,1.276 -1.467,2.117 -2.743,1.878 z"
id="path162" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 295.985,129.891 c -2.559,-0.803 -5.481,-2.802 -3.529,-5.832 2.278,-3.537 6.42,-1.396 6.688,2.135 0,0.455 -0.129,0.88 -0.353,1.24 0.013,0.201 10e-4,0.407 -0.04,0.614 -0.255,1.273 -1.493,2.098 -2.766,1.843 z"
id="path164" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 304.59,127.023 c -1.264,-1.217 -2.255,-2.819 -0.603,-4.278 2.369,-2.09 7.775,0.524 7.487,3.692 -0.203,2.232 -2.984,2.327 -4.582,2.455 -1.134,0 -2.08,-0.801 -2.302,-1.869 z"
id="path166" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 323.257,130.982 c -2.279,-0.159 -6.378,-1.101 -4.858,-4.386 0.991,-2.14 4.238,-2.946 6.174,-1.692 1.238,0.802 1.592,1.996 1.73,3.379 0,1.059 -0.701,1.956 -1.664,2.249 -0.388,0.283 -0.865,0.45 -1.382,0.45 z"
id="path168" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 347.404,135.83 c 1.612,-0.767 3.365,-1.131 4.585,0.341 2.392,2.885 -2.249,7.396 -5.332,6.304 -0.484,-0.172 -0.87,-0.424 -1.178,-0.735 -0.61,-0.108 -1.176,-0.456 -1.546,-1.011 -0.639,-0.96 -0.481,-2.217 0.32,-2.991 0.145,-1.159 1.134,-2.056 2.332,-2.056 0.288,0 0.563,0.053 0.819,0.148 z"
id="path170" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 333.793,128.576 c 0.106,-0.45 0.326,-0.886 0.643,-1.264 0.917,-0.917 2.405,-0.917 3.323,0 0.114,0.114 0.213,0.237 0.298,0.366 l 0.526,0.32 c 5.453,4.065 -5.784,10.141 -7.365,4.423 -0.584,-2.109 0.855,-3.252 2.575,-3.845 z"
id="path172" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 354.483,150.534 c -1.804,-0.746 -3.844,-2.061 -2.933,-4.384 1.936,-4.935 11.861,-1.797 9.861,3.125 -1.051,2.586 -4.114,2.004 -6.278,1.367 -0.216,-0.005 -0.433,-0.04 -0.65,-0.108 z"
id="path174" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 360.204,158.846 c -0.105,-2.008 0.136,-4.362 2.498,-4.857 3.39,-0.711 8.413,5.566 5.38,8.381 -2.079,1.931 -5.001,-0.248 -6.843,-1.316 -0.755,-0.503 -1.125,-1.365 -1.035,-2.208 z"
id="path176" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.681,173.358 c -1.285,-1.236 -3.668,-3.339 -2.048,-5.343 2.096,-2.594 8.802,-1.036 8.998,2.547 0.132,2.399 -2.365,2.849 -4.335,3.002 -0.808,0.455 -1.843,0.405 -2.615,-0.206 z"
id="path178" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.97,179.521 c 0.668,-1.088 1.676,-1.799 3.206,-1.515 3.973,0.735 4.505,7.545 0.586,8.807 -1.584,0.509 -2.862,0.193 -3.827,-0.585 -0.49,-0.268 -0.875,-0.705 -1.074,-1.234 -0.569,-0.907 -0.927,-2.018 -1.07,-3.13 0,-1.24 0.961,-2.256 2.179,-2.343 z"
id="path180" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.882,195.121 c 10e-4,-0.008 0.003,-0.016 0.004,-0.024 -0.889,-1.11 -1.154,-2.552 -1.171,-3.948 0.08,-1.296 1.194,-2.282 2.49,-2.202 0.692,0.042 1.294,0.381 1.695,0.883 0.619,-0.226 1.356,-0.221 2.233,0.125 2.109,0.832 3.322,3.976 1.812,5.832 -0.724,0.89 -1.832,1.239 -2.977,1.206 -0.502,0.564 -1.264,0.875 -2.067,0.768 -1.287,-0.171 -2.191,-1.353 -2.019,-2.64 z"
id="path182" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 366.711,243.253 c -2.14,-1.948 -2.704,-4.666 10e-4,-6.518 3.673,-2.514 8.917,1.307 7.159,5.589 -0.739,1.801 -2.816,2.734 -4.647,2.049 -0.488,-0.183 -0.883,-0.437 -1.205,-0.746 -0.448,0.007 -0.902,-0.113 -1.308,-0.374 z"
id="path184" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 363.062,253.311 c 0.952,-2.018 2.271,-4.97 5.094,-3.857 3.461,1.365 4.881,8.753 1.239,10.632 -2.308,1.191 -4.24,-0.67 -5.954,-2.015 -0.824,-0.823 -0.909,-2.105 -0.255,-3.022 -0.254,-0.523 -0.314,-1.141 -0.124,-1.738 z"
id="path186" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 364.477,277.674 c -0.51,-1.449 -0.608,-2.979 1.097,-3.86 2.79,-1.442 7.426,1.83 6.267,4.997 -0.809,2.211 -3.385,2.253 -5.347,2.42 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.442 0.121,-0.854 0.333,-1.207 z"
id="path188" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 368.32,291.409 c 0.229,-2.722 1.853,-4.523 4.755,-4.29 2.14,0.172 5.586,1.881 5.324,4.485 -0.082,0.812 -0.473,1.503 -1.105,1.974 -0.897,2.04 -3.853,3.126 -5.815,1.565 -0.436,-0.346 -0.755,-0.844 -0.913,-1.386 -1.25,-0.055 -2.246,-1.085 -2.246,-2.348 z"
id="path190" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 377.875,299.502 c 1.985,-2.181 5.125,-4.315 8.258,-3.062 4.838,1.933 2.627,6.95 -1.028,8.511 -1.377,0.588 -3.667,0.859 -4.576,-0.729 l -0.482,-0.954 -0.009,-0.031 c -0.135,-0.074 -0.263,-0.16 -0.38,-0.258 -0.297,-0.035 -0.592,-0.127 -0.869,-0.281 -1.135,-0.63 -1.544,-2.061 -0.914,-3.196 z"
id="path192" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 392.26,312.253 c -0.088,-0.028 -0.176,-0.057 -0.265,-0.088 -0.489,-0.021 -0.978,-0.067 -1.465,-0.124 -1.004,-0.287 -1.669,-1.185 -1.704,-2.175 -0.354,-0.697 -0.408,-1.54 0.029,-2.546 1.312,-3.02 5.725,-3.056 7.872,-1.031 1.485,1.401 1.599,3.812 -0.297,4.949 -0.871,0.523 -1.805,0.784 -2.763,0.887 -0.43,0.181 -0.917,0.235 -1.407,0.128 z"
id="path194" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 416.208,335.904 c -1.787,-1.168 -5.454,-3.337 -3.163,-5.92 1.933,-2.177 6.675,-0.549 8.742,0.445 1.594,0.766 3.03,2.821 1.53,4.446 -1.343,1.456 -3.449,1.223 -5.255,1.33 -0.12,0 -0.237,-0.008 -0.352,-0.025 -0.5,0.076 -1.027,-0.009 -1.502,-0.276 z"
id="path196" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 399.133,321.246 c 0.205,-2.1 1.113,-4.444 3.573,-4.702 2.95,-0.308 7.779,2.181 5.944,5.797 -1.292,2.546 -4.799,2.423 -7.167,2.585 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.231 0.033,-0.453 0.095,-0.664 -0.062,-0.211 -0.095,-0.435 -0.095,-0.666 z"
id="path198" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 426.369,342.627 c 1.879,-3.041 6.734,-5.137 8.725,-0.834 1.964,4.248 -2.58,8.094 -6.659,6.823 -1.794,-0.559 -2.773,-1.822 -3.223,-3.558 -0.167,-1 0.324,-1.958 1.157,-2.431 z"
id="path200" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 438.823,359.598 c -2.112,-2.05 -2.069,-5.044 0.695,-6.536 2.849,-1.537 10.774,-2.028 9.626,3.426 -0.612,2.904 -4.519,5.618 -7.434,4.246 -0.372,-0.174 -0.685,-0.389 -0.947,-0.633 -0.665,0.125 -1.379,-0.036 -1.94,-0.503 z"
id="path202" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 449.504,367.991 c 0.459,-0.329 1.067,-0.468 1.873,-0.309 0.257,0.051 0.493,0.131 0.711,0.237 0.937,0.219 1.782,0.744 2.377,1.668 1.118,1.733 0.507,3.586 0.005,5.409 -0.472,1.209 -1.835,1.807 -3.044,1.335 -0.049,-0.019 -0.097,-0.04 -0.143,-0.062 -0.622,0.139 -1.337,0.049 -2.137,-0.361 -2.418,-1.242 -5.124,-4.361 -2.165,-6.683 0.713,-0.56 1.597,-0.997 2.523,-1.234 z"
id="path204" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 460.887,383.928 c 3.505,0.279 5.866,5.971 1.895,7.43 -0.798,0.293 -1.833,0.308 -2.896,0.097 -0.212,0.063 -0.435,0.097 -0.668,0.097 -0.841,0 -1.58,-0.443 -1.995,-1.108 -1.795,-1.054 -3.056,-2.75 -2.397,-4.745 0.655,-1.985 2.585,-2.299 4.392,-2.467 0.653,0 1.243,0.266 1.669,0.696 z"
id="path206" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 467.474,406.964 c -1.798,-0.783 -4.577,-1.752 -4.449,-4.19 0.243,-4.596 7.857,-3.291 9.328,-0.216 0.799,1.672 -0.362,3.365 -1.397,4.581 -0.917,0.918 -2.406,0.918 -3.323,0 -0.056,-0.056 -0.11,-0.115 -0.159,-0.175 z"
id="path208" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 471.216,427.057 c -0.902,0.345 -1.961,0.109 -2.624,-0.667 -1.052,-1.672 -2.519,-4.08 -0.899,-5.961 3.011,-3.497 11.708,-1.604 9.869,3.93 -0.874,2.629 -3.395,3.192 -5.823,2.897 -0.185,-0.046 -0.361,-0.114 -0.523,-0.199 z"
id="path210" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 475.942,438.485 c 1.04,0.598 1.771,1.552 1.635,3.044 -0.365,3.995 -4.595,6.317 -8.19,4.632 -2.125,-0.996 -2.207,-3.938 -1.071,-5.677 1.332,-2.04 2.826,-3.25 5.14,-3.829 1.185,-0.098 2.236,0.701 2.486,1.83 z"
id="path212" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 471.258,456.124 c 0.386,-0.77 1.183,-1.299 2.104,-1.299 0.102,0.012 0.202,0.024 0.303,0.04 0.752,-0.142 1.498,0.094 2.029,0.584 1.757,0.801 2.979,2.317 2.715,4.613 -0.475,4.132 -7.629,3.931 -8.864,0.393 -0.687,-1.966 0.309,-3.341 1.713,-4.331 z"
id="path214" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.05,136.106 -0.139,0.028 c -1.915,0.308 -2.917,-4.254 -0.852,-4.624 l 0.028,-0.004 0.013,-0.002 0.237,-0.046 0.543,-0.107 c 0.244,-0.049 0.487,-0.057 0.721,-0.031 l 0.122,-0.014 c 1.298,0 2.35,1.052 2.35,2.35 0,1.298 -1.052,2.35 -2.35,2.35 l -0.243,0.031 -0.43,0.069 z m -0.934,-4.603 0.138,-0.017 -0.077,0.007 -0.061,0.01 z"
id="path216" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 369.676,143.446 c -0.73,-1.424 -1.183,-3.038 0.349,-4.226 2.433,-1.888 7.486,0.678 7.014,3.865 -0.369,2.494 -3.007,2.667 -5.016,2.848 -1.298,0 -2.351,-1.052 -2.351,-2.35 0,-0.046 0.002,-0.091 0.004,-0.137 z"
id="path218" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 377.559,149.633 c 2.461,0.216 5.758,1.845 3.748,4.84 -2.11,3.146 -5.866,0.999 -6.098,-2.108 0,-0.065 0.002,-0.128 0.007,-0.191 -0.005,-0.062 -0.007,-0.127 -0.007,-0.191 0,-1.298 1.052,-2.35 2.35,-2.35 z"
id="path220" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 379.959,162.946 c 1.656,-2.842 7.349,-4.245 7.766,0.257 0.217,2.345 -1.576,3.53 -3.67,3.906 l -0.78,0.056 -0.127,0.004 c -0.834,0.31 -1.808,0.128 -2.478,-0.543 -0.444,-0.587 -0.645,-1.201 -0.64,-1.772 -0.282,-0.576 -0.328,-1.266 -0.071,-1.908 z"
id="path222" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 383.505,173.306 c 0.408,-0.464 0.965,-0.796 1.716,-0.895 2.871,-0.379 5.553,2.274 4.671,5.22 -0.998,3.337 -5.939,2.471 -7.795,0.519 -0.68,-0.716 -0.877,-1.557 -0.97,-2.495 0,-1.298 1.052,-2.35 2.35,-2.35 0.01,0 0.018,0.001 0.028,0.001 z"
id="path224" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 382.848,189.533 c -0.692,-2.067 -0.586,-4.342 1.826,-5.219 2.908,-1.057 6.147,1.237 6.537,4.197 0.597,4.515 -5.16,4.508 -7.677,2.551 -0.426,-0.425 -0.655,-0.972 -0.686,-1.529 z"
id="path226" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 385.826,251.827 c 0.448,-0.282 0.994,-0.415 1.56,-0.34 2.588,0.689 4.562,2.821 3.173,5.606 -1.853,3.717 -9.312,3.173 -9.144,-1.467 0.081,-2.231 2.086,-3.249 3.969,-3.759 0.149,-0.028 0.296,-0.04 0.442,-0.04 z"
id="path228" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 386.265,263.315 c 0.335,-0.124 0.705,-0.173 1.085,-0.128 2.768,0.504 5.201,2.744 2.977,5.488 -1.55,1.913 -5.537,3.367 -7.431,1.148 -1.53,-1.793 -0.309,-3.859 0.604,-5.606 0.615,-0.922 1.768,-1.269 2.765,-0.902 z"
id="path230" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 397.797,276.344 c 0.283,0.115 0.55,0.287 0.779,0.517 1.776,2.071 2.07,4.986 -0.942,6.03 -2.414,0.836 -6.668,-0.274 -6.38,-3.45 0.19,-2.092 2.279,-2.926 3.902,-3.74 0.953,-0.378 2.005,-0.089 2.641,0.643 z"
id="path232" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 406.747,287.629 c 1.08,1.17 2.031,2.637 0.739,4.121 -1.914,2.197 -6.854,0.34 -7.576,-2.23 -0.801,-2.85 2.146,-3.659 4.282,-4.053 1.292,-0.117 2.435,0.836 2.552,2.129 10e-4,0.011 0.002,0.022 0.003,0.033 z"
id="path234" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 412.436,296.028 c 0.519,-0.573 1.31,-0.88 2.129,-0.744 0.249,0.042 0.48,0.121 0.693,0.231 1.15,0.091 2.087,1.018 2.157,2.203 0.073,1.233 -0.819,2.301 -2.022,2.467 -0.938,1.183 -2.313,1.838 -3.894,0.742 -1.431,-0.991 -1.405,-3.103 -0.147,-4.23 0.334,-0.299 0.698,-0.511 1.084,-0.669 z"
id="path236" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 424.19,304.681 c 0.203,0.103 0.399,0.224 0.582,0.359 0.918,0.917 0.918,2.406 0,3.323 -0.127,0.128 -0.266,0.239 -0.413,0.33 l -0.242,0.261 c -2.285,2.125 -7.717,-1.007 -5.61,-4.009 0.935,-1.333 2.532,-1.156 3.947,-1.031 0.688,0 1.306,0.296 1.736,0.767 z"
id="path238" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 425.898,314.312 c 0.185,-0.588 0.599,-1.104 1.194,-1.401 0.692,-0.345 1.472,-0.317 2.113,0.008 1.012,0.178 1.825,1.009 1.931,2.082 0.084,0.84 -0.287,1.622 -0.913,2.101 -0.393,0.75 -1.151,1.242 -2.365,1.144 -1.934,-0.158 -2.884,-2.345 -1.96,-3.934 z"
id="path240" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 435.675,320.542 c 0.082,-0.038 0.168,-0.072 0.255,-0.102 1.232,-0.41 2.562,0.256 2.972,1.488 0.528,2.539 -0.813,5.337 -3.869,4.182 -2.886,-1.091 -2.514,-4.572 0.198,-5.502 0.149,-0.037 0.297,-0.058 0.444,-0.066 z"
id="path242" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 445.007,334.777 -0.167,0.037 c -0.586,0.573 -1.399,0.778 -2.147,0.614 -1.271,0.116 -2.358,-0.497 -2.781,-1.725 -0.563,-1.638 1.098,-2.364 2.597,-2.923 l -0.176,-0.027 -0.231,0.013 -0.037,0.004 0.215,-0.061 0.377,-0.097 0.336,-0.011 c 0.375,-0.139 0.721,-0.272 0.995,-0.412 1.267,-0.282 2.522,0.517 2.804,1.784 0.281,1.267 -0.518,2.522 -1.785,2.804 z"
id="path244" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 450.342,340.548 c 1.425,-0.225 3.788,0.036 3.482,2.21 -0.224,1.591 -1.118,2.111 -2.484,2.468 -1.231,0.41 -2.562,-0.256 -2.972,-1.488 -0.302,-0.906 -0.021,-1.868 0.64,-2.475 0.341,-0.366 0.802,-0.626 1.334,-0.715 z"
id="path246" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 460.356,355.597 -0.009,0.25 c 0,1.298 -1.052,2.35 -2.35,2.35 -1.298,0 -2.35,-1.052 -2.35,-2.35 0,-0.002 0,-0.003 0,-0.005 -0.085,-0.243 -0.13,-0.502 -0.13,-0.774 0,-0.511 0.162,-0.984 0.438,-1.369 0.364,-1.387 1.147,-2.565 2.921,-2.084 2.102,0.571 2.299,2.497 1.48,3.982 z"
id="path248" />
<path
style="fill:#363a40;stroke:#363a40;stroke-width:0.500094"
d="m 253.064,212.441 c -5.171,4.318 -10.465,7.777 -10.015,15.252 0.375,6.204 7.982,11.066 13.918,10.177 7.031,-1.054 13.803,-6.459 17.537,-12.357 1.513,-2.39 3.1,-5.964 1.417,-8.698 -1.686,-2.738 -5.801,-6.44 -9.071,-7.093 -4.592,-0.918 -9.509,1.309 -13.786,2.719 z"
id="path250" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 257.655,218.342 c 0.316,-0.529 0.892,-0.885 1.553,-0.885 4.255,-0.088 8.971,-0.311 9.321,4.987 0.35,5.292 -4.997,8.682 -9.95,7.972 -3.979,-0.57 -6.853,-4.746 -5.027,-8.579 0.897,-1.881 2.39,-2.854 4.103,-3.495 z"
id="path252" />
<path
style="fill:#676f79;stroke:#676f79;stroke-width:0.500094"
d="m 261.148,221.058 c -1.818,0.434 -5.856,1.65 -4.226,4.412 1.493,2.531 5.837,1.327 7.435,-0.466 0.595,-0.668 1.069,-2.976 0.261,-3.602 -0.684,-0.529 -1.77,-0.596 -2.852,-0.539 -0.187,0.099 -0.395,0.167 -0.618,0.195 z"
id="path254" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 339.682,197.571 c 1.215,0.322 2.419,0.677 3.6,1.078 l 0.447,0.078 c 0.22,0.081 0.427,0.183 0.62,0.299 5.77,2.13 10.813,5.503 13.201,11.816 3.645,9.638 -1.143,20.015 -10.924,23.128 -9.795,3.118 -21.6,-0.139 -29.443,-6.387 -7.77,-6.189 -6.575,-17.605 1.339,-23.199 5.546,-3.921 11.631,-6.957 18.577,-6.822 l 0.935,0.165 c 0.514,-0.173 1.075,-0.235 1.648,-0.156 z"
id="path256" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 367.648,208.65 c -0.828,-1.835 -1.187,-4.404 1.262,-5.25 3.401,-1.173 8.014,1.285 8.553,4.948 0.465,3.162 -3.471,4.728 -5.774,2.88 l -0.593,-0.542 -0.14,-0.154 c -0.578,-0.05 -1.127,-0.313 -1.528,-0.75 -0.713,-0.072 -1.383,-0.47 -1.78,-1.132 z"
id="path258" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 390.23,199.555 c 1.369,0.808 2.247,2.179 1.193,3.934 -1.386,2.308 -4.828,3.856 -6.935,1.592 -2.861,-3.076 0.102,-6.767 3.509,-7.144 1.042,0 1.925,0.679 2.233,1.618 z"
id="path260" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 389.354,226.668 c 0.194,0.04 0.387,0.105 0.573,0.198 1.94,1.137 3.546,3.258 1.817,5.377 -1.657,2.033 -5.761,2.287 -7.14,-0.19 -1.091,-1.96 0.14,-3.683 1.202,-5.303 0.828,-1 2.309,-1.14 3.309,-0.312 0.086,0.072 0.165,0.149 0.239,0.23 z"
id="path262" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 387.935,238.324 c 1.766,0.591 2.974,2.125 2.714,4.332 -0.485,4.124 -6.678,2.461 -7.65,-0.568 -0.778,-2.424 0.721,-4.151 2.891,-4.897 0.88,-0.176 1.738,0.32 2.045,1.133 z"
id="path264" />
<path
style="fill:#363a40;stroke:#363a40;stroke-width:0.500094"
d="m 341.837,205.679 c -0.206,-0.037 -0.411,-0.093 -0.613,-0.168 -8.084,-1.745 -19.919,1.53 -22.156,10.598 -0.913,3.702 3.72,7.021 6.318,8.344 5.656,2.881 12.88,4.524 19.114,2.605 6.725,-2.07 9.018,-9.937 5.181,-15.739 -1.977,-2.989 -4.74,-4.555 -7.844,-5.64 z"
id="path266" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 365.999,225.171 c -0.748,-0.677 -1.119,-1.572 -0.487,-2.786 1.09,-2.093 4.368,-1.388 6.141,-1.099 1.565,0.255 3.25,1.189 2.963,3.028 -0.34,2.178 -3.015,2.23 -5.019,2.25 -0.292,0.063 -0.6,0.072 -0.907,0.016 -0.189,0.008 -0.364,0.018 -0.521,0.035 -0.977,0 -1.816,-0.595 -2.17,-1.444 z"
id="path268" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 385.323,213.679 c 0.285,-0.221 0.619,-0.373 0.974,-0.444 0.344,-0.127 0.702,-0.23 1.064,-0.312 1.161,-0.11 2.203,0.643 2.493,1.734 1.519,1.098 2.718,2.616 1.919,4.525 -1.616,3.856 -8.376,2.319 -8.613,-1.73 -0.107,-1.816 0.829,-3.026 2.163,-3.773 z"
id="path270" />
<path
style="fill:#000000;stroke:#000000;stroke-width:0.500094"
d="m 335.279,211.744 c 0.345,-0.328 0.818,-0.52 1.331,-0.496 0.344,0.029 0.689,0.064 1.037,0.104 0.809,-0.098 1.623,-0.169 2.427,-0.233 0.776,0 1.437,0.49 1.694,1.177 1.986,0.819 3.491,2.272 3.72,4.956 0.668,7.847 -9.275,8.891 -14.504,5.611 -2.58,-1.618 -3.987,-5 -1.947,-7.541 1.66,-2.067 3.868,-3.051 6.242,-3.578 z"
id="path272" />
<path
style="fill:#676f79;stroke:#676f79;stroke-width:0.500094"
d="m 337.752,214.937 c -2.207,0.259 -4.337,0.822 -5.907,2.663 -0.566,0.664 0.195,1.399 0.705,1.857 2.565,2.304 11.124,2.53 9.15,-2.767 -0.524,-1.406 -2.405,-1.657 -3.948,-1.753 z"
id="path274" />
</g>
<g
id="g276" />
</svg>
doc/hdlg/fig/pulse-led.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="290.5"
height="148"
id="svg3211"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="pulse-led.svg">
<defs
id="defs3213">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path4095"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3142"
style="overflow:visible">
<path
id="path3144"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8284271"
inkscape:cx="209.7957"
inkscape:cy="9.6507271"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
showguides="true"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid3236"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
spacingx="1px"
spacingy="1px"
originx="40px"
originy="-744px" />
</sodipodi:namedview>
<metadata
id="metadata3216">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(40,-160.36218)">
<rect
y="227.36218"
x="60"
height="44.999996"
width="75"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:3, 1;stroke-dashoffset:0"
rx="5"
ry="5" />
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="m 147.81815,161.36218 0,146"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="142.5"
y="176.36218"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="142.5"
y="176.36218"
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="176.36218"
x="152.5"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start;opacity:0.3"
y="176.36218"
x="152.5"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<path
transform="matrix(2,0,0,2,122.78516,142.80416)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5613"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 102.16535,242.36218 5.62991,0 0,5.37004 8.85827,0 0,-5.37004 10.51182,0"
id="path5345"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccccc" />
<path
inkscape:connector-curvature="0"
id="path5357"
d="m 60,257.36218 75,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="cc" />
<g
id="g5367"
transform="translate(-524.68504,108.54325)">
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 602.36221,141.73229 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
id="path5323"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5325"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.24999996,0,0,0.24999996,581.98819,119.58663)" />
</g>
<path
sodipodi:nodetypes="cc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 30,257.36218 25,0"
id="path4313"
inkscape:connector-curvature="0" />
<rect
y="162.36218"
x="-40"
height="145"
width="65"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m 25,162.36218 0,145"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="20"
y="260.36218"
id="text4969"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4971"
x="20"
y="260.36218"
style="text-align:end;text-anchor:end">led_pulse_o</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4973"
y="172.36218"
x="22.294922"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="172.36218"
x="22.294922"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold;text-align:end;text-anchor:end">Conv.</tspan><tspan
y="184.86218"
x="22.294922"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold;text-align:end;text-anchor:end">common</tspan><tspan
y="197.36218"
x="22.294922"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold;text-align:end;text-anchor:end">gateware</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="190"
y="202.36218"
id="text4336"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="190"
y="202.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4338">RS-485 output</tspan><tspan
sodipodi:role="line"
x="190"
y="209.86218"
style="font-size:6px;font-weight:normal;text-align:center;text-anchor:middle"
id="tspan4340">(rear panel)</tspan></text>
<path
sodipodi:nodetypes="ccc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 60,162.36218 0,40 100,0"
id="path4344"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path4348"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,122.78516,87.804158)" />
<text
sodipodi:linespacing="125%"
id="text3769"
y="236.36218"
x="83"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="236.36218"
x="83"
sodipodi:role="line"
id="tspan4961"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4965">6x</tspan> LED logic</tspan></text>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 30.511816,247.73222 5.629914,0 0,-5.37004 8.85827,0 0,5.37004 10.511816,0"
id="path4424"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccccc" />
<g
id="g4554"
style="opacity:0.3"
transform="translate(-0.57153918,-0.62987445)">
<path
inkscape:connector-curvature="0"
id="path3757"
d="m 179.57154,251.27559 0,17.71646 18,-11 -18,-10 z"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="ccccc" />
<path
transform="matrix(0.24999892,0,0,0.24999892,159.93786,228.7599)"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
sodipodi:ry="7.0866141"
sodipodi:rx="7.0866141"
sodipodi:cy="116.92912"
sodipodi:cx="159.44882"
id="path3759"
style="fill:none;stroke:#000000;stroke-width:2.00000858;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
inkscape:connector-curvature="0"
id="path3607"
d="m 182.87424,259.80552 3.62692,0 1.20898,-3.62693 2.41795,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 190.12809,256.17859 -3.62692,0 -1.20898,3.62693 -2.41795,0"
id="path3609"
inkscape:connector-curvature="0" />
</g>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 225.5,97 39,0"
id="path4562"
inkscape:connector-curvature="0"
transform="translate(-85.5,160.36218)"
sodipodi:nodetypes="cc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 325.5,97 5,0 0,15"
id="path4566"
inkscape:connector-curvature="0"
transform="translate(-85.5,160.36218)"
sodipodi:nodetypes="ccc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 286.5,97 13,0 2,-3 3,6 3,-6 3,6 3,-6 3,6 3,-6 3,6 2,-3 1,0"
id="path4570"
inkscape:connector-curvature="0"
transform="translate(-85.5,160.36218)" />
<g
transform="matrix(0,-1,1,0,28.858298,338.07121)"
id="g4128"
style="opacity:0.3">
<g
style="stroke-width:0.23634885;stroke-miterlimit:4;stroke-dasharray:none"
id="g6474"
transform="matrix(0,-1.0577593,1.0577593,0,-192.41869,279.87711)">
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path6476"
d="m 60.283363,228.95835 -5.052989,8.23731 10.049478,0 z"
style="fill:#000000;fill-opacity:1;stroke:#000000;stroke-width:0.23634885;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
transform="matrix(0,0.47269769,-0.47269769,0,162.45305,212.20922)"
inkscape:connector-curvature="0"
id="path6480"
d="m 67.322842,216.20147 -14.173236,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path6482"
d="m 60.255113,232.15897 0,-11.76127"
style="fill:none;stroke:#000000;stroke-width:0.47269768px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 325.5,137 10,0"
id="path4601"
inkscape:connector-curvature="0"
transform="matrix(-0.94539467,0,0,-0.94539467,372.70805,349.91677)" />
</g>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path6484"
d="m 56.850744,210.82674 -3.543309,-3.60447"
style="fill:none;stroke:#000000;stroke-width:0.50000036px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path6486"
d="m 51.53578,210.82674 -3.533467,-3.63435"
style="fill:none;stroke:#000000;stroke-width:0.50000036px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path3128"
d="m 49.6063,212.59842 0,7.08662"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
</g>
</g>
</svg>
doc/hdlg/fig/rs485-inp.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="310.41797"
height="162"
id="svg4040"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="rs485-inp.svg">
<defs
id="defs4042">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path3992"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker4023"
style="overflow:visible">
<path
id="path4025"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-9"
style="overflow:visible">
<path
id="path4441"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-6"
style="overflow:visible">
<path
id="path3992-3"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker5356"
style="overflow:visible">
<path
id="path5358"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3133"
style="overflow:visible">
<path
id="path3135"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="198.529"
inkscape:cy="68.648012"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="true"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid4556"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="-29.582031px"
originy="-859px" />
</sodipodi:namedview>
<metadata
id="metadata4045">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-29.582031,-31.362183)">
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="M 80,32.362183 80,192.36218"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="85"
y="47.362183"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="85"
y="47.362183"
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="47.362183"
x="75"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end;opacity:0.3"
y="47.362183"
x="75"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<path
style="opacity:0.3;fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 194.19685,103.76113 c 5.16063,6.88084 5.16063,10.32125 0,17.20209 12.04146,0 20.64251,0 25.80315,-8.60104 -5.16064,-8.60105 -13.76169,-8.60105 -25.80315,-8.60105 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<g
id="g5490">
<rect
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3779"
width="80"
height="35"
x="95"
y="67.362183" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="135.16113"
y="81.217163"
id="text3769"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="135.16113"
y="81.217163"
id="tspan3773"
style="font-size:10px;text-align:center;text-anchor:middle">TTL/TTL-BAR</tspan><tspan
id="tspan3777"
sodipodi:role="line"
x="135.16113"
y="93.717163"
style="font-size:10px;text-align:center;text-anchor:middle">input logic</tspan></text>
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path5544"
d="m 180,85.36218 5,0 0,22 5,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
</g>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 180,139.36218 5,0 0,-22 5,0"
id="path5546"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<rect
y="117.36218"
x="90"
height="70"
width="84.999954"
id="rect3779-9"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:6, 2;stroke-dashoffset:0"
rx="8.858223"
ry="8.858223" />
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 142,130.36218 c 0,8.85826 0,9.14173 0,18 12.04146,0 18,-3.68503 18,-9 0,-5.31496 -5.95854,-9 -18,-9 z"
id="path3936-1"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
transform="matrix(0.24999996,0,0,0.24999996,92.36615,138.12991)"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
sodipodi:ry="7.0866141"
sodipodi:rx="7.0866141"
sodipodi:cy="116.92912"
sodipodi:cx="159.44882"
id="path5433"
style="fill:none;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 160,139.36218 15,0"
id="path5440"
inkscape:connector-curvature="0" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 134,167.36218 4,0 0,-23 4,0"
id="path5450"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path5452"
d="m 112,158.36218 c 0,8.85826 0,9.14173 0,18 12.04146,0 18,-3.68503 18,-9 0,-5.31496 -5.95854,-9 -18,-9 z"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.56;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 142,134.36218 -72,0"
id="path5467"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 112,172.36218 -42,0"
id="path5469"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 100,134.36218 0,28 12,0"
id="path5471"
inkscape:connector-curvature="0" />
<path
transform="translate(-9.983238,150.85034)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path4618"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.56;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="52"
y="133.36218"
id="text5484"
sodipodi:linespacing="125%"><tspan
id="tspan5488"
sodipodi:role="line"
x="52"
y="133.36218"
style="font-size:6px;text-align:center;text-anchor:middle">RS-485</tspan><tspan
sodipodi:role="line"
x="52"
y="140.86218"
style="font-size:6px;text-align:center;text-anchor:middle"
id="tspan5523">transceiver</tspan></text>
<text
sodipodi:linespacing="125%"
id="text5499"
y="170.36218"
x="52"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="170.36218"
x="52"
sodipodi:role="line"
id="tspan5501">failsafe</tspan><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="177.86218"
x="52"
sodipodi:role="line"
id="tspan5525">transceiver</tspan></text>
<path
transform="matrix(2,0,0,2,54.78516,19.804161)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5617"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5521"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,54.78516,57.804161)" />
<rect
y="32.362183"
x="270"
height="160"
width="70"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m 270,32.362183 0,159.999997"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="275"
y="115.36218"
id="text4969"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4971"
x="275"
y="115.36218">pulse_i</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4973"
y="47.362183"
x="275"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="47.362183"
x="275"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold">Conv.</tspan><tspan
y="59.862183"
x="275"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold">common</tspan><tspan
y="72.362183"
x="275"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold">gateware</tspan></text>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m 225,112.36218 10,0"
id="path3838"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<rect
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect5291"
width="9.84375"
height="35"
x="240.15625"
y="93.441269" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="240"
y="142.36218"
id="text5293"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="240"
y="142.36218"
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan5297">First pulse</tspan><tspan
id="tspan5301"
sodipodi:role="line"
x="240"
y="154.86218"
style="font-size:10px;text-align:center;text-anchor:middle">inhibit</tspan></text>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path5305"
d="m 255,112.36218 10,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)" />
<path
sodipodi:type="arc"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.56;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path3880"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(28.016762,184.07868)" />
<text
sodipodi:linespacing="125%"
id="text3769-5"
y="127.36218"
x="115"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="127.36218"
x="115"
sodipodi:role="line"
id="tspan4961"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4965">6x</tspan> input logic</tspan></text>
<g
id="g3909">
<rect
y="162.36218"
x="273"
height="13"
width="65"
id="rect3897"
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="274.93604"
y="172.50232"
id="text3893"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3895"
x="274.93604"
y="172.50232">LSR.REARFS</tspan></text>
</g>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 108.41797,136 37,0"
id="path3916"
inkscape:connector-curvature="0"
transform="translate(29.582031,31.362183)" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)"
d="m 150.41797,136 85,0"
id="path3918"
inkscape:connector-curvature="0"
transform="translate(29.582031,31.362183)" />
</g>
</svg>
doc/hdlg/fig/switches.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="226.56073"
height="122"
id="svg4040"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="switches.svg">
<defs
id="defs4042">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path3992"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker4023"
style="overflow:visible">
<path
id="path4025"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-9"
style="overflow:visible">
<path
id="path4441"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-6"
style="overflow:visible">
<path
id="path3992-3"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker5356"
style="overflow:visible">
<path
id="path5358"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3133"
style="overflow:visible">
<path
id="path3135"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-7"
style="overflow:visible">
<path
id="path3992-6"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="5.6"
inkscape:cx="120.05079"
inkscape:cy="53.256621"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="false"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid4556"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="-123.43927px"
originy="-844px" />
</sodipodi:namedview>
<metadata
id="metadata4045">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-123.43927,-86.362183)">
<rect
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect4288"
width="2.9879105"
height="7.4697757"
x="177.133"
y="156.15752" />
<path
inkscape:connector-curvature="0"
id="path4290"
d="m 178.63401,156.11199 0,-6.67727"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path5106"
d="m 178.62573,171.09707 0,-7.4494 0.001,7.4494"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path5108"
d="m 175.63903,171.84405 2.98792,3.73489 0,3.73489"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 177.13299,179.31383 2.98791,0"
id="path5110"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path5112"
d="m 178.62695,167.36218 16.37305,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="cc" />
<path
transform="matrix(0.42162733,0,0,0.42162733,132.25501,174.41032)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path5114"
style="opacity:0.3;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<text
xml:space="preserve"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="149"
y="156.36218"
id="text5024"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="149"
y="156.36218"
id="tspan5026"
style="font-style:normal;text-align:center;text-anchor:middle">General-purpose</tspan><tspan
id="tspan5028"
sodipodi:role="line"
x="149"
y="164.10144"
style="font-style:normal;text-align:center;text-anchor:middle">switches</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 215,167.36218 35,0"
id="path4051"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="m 195,87.362183 0,119.999997"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="200"
y="102.36218"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="200"
y="102.36218"
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="102.36218"
x="190"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end;opacity:0.3"
y="102.36218"
x="190"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<rect
y="87.362183"
x="270"
height="119.99999"
width="80"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m 270,87.362183 0,119.999997"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<text
sodipodi:linespacing="125%"
id="text4973"
y="102.36218"
x="275"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="102.36218"
x="275"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold">Conv.</tspan><tspan
y="114.86218"
x="275"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold">common</tspan><tspan
y="127.36218"
x="275"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold">gateware</tspan></text>
<g
id="g3909">
<rect
y="162.36218"
x="273"
height="13"
width="72"
id="rect3897"
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="274.93604"
y="172.50232"
id="text3893"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3895"
x="274.93604"
y="172.50232">SR.SWITCHES</tspan></text>
</g>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)"
d="m 255,167.36218 10,0"
id="path3918"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<rect
y="152.36218"
x="215"
height="55"
width="35.000076"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:3, 1;stroke-dashoffset:2.15"
rx="5"
ry="5" />
<g
transform="matrix(0.61914096,0,0,0.61914096,137.89186,92.772793)"
id="g3783"
style="fill:#ffffff;fill-opacity:1">
<path
inkscape:connector-curvature="0"
id="path3785"
d="m 141.73228,113.3858 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
transform="matrix(0.24999996,0,0,0.24999996,121.67006,91.240144)"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
sodipodi:ry="7.0866141"
sodipodi:rx="7.0866141"
sodipodi:cy="116.92912"
sodipodi:cx="159.44882"
id="path3787"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
</g>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4570"
d="m 200,167.36218 10,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4591"
d="m 215,192.36216 35,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<g
style="fill:#ffffff;fill-opacity:1"
id="g4593"
transform="matrix(0.61914096,0,0,0.61914096,137.89186,117.77277)">
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 141.73228,113.3858 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
id="path4595"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path4597"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.24999996,0,0,0.24999996,121.67006,91.240144)" />
</g>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4599"
d="m 255,192.36218 10,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3133)"
d="m 200,192.36218 10,0"
id="path4601"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<g
id="g4603"
transform="translate(0,23)">
<rect
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect4605"
width="72"
height="13"
x="273"
y="162.36218" />
<text
sodipodi:linespacing="125%"
id="text4607"
y="172.50232"
x="292.74756"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="172.50232"
x="292.74756"
id="tspan4609"
sodipodi:role="line">MSWR</tspan></text>
</g>
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5521"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,169.78516,52.804161)" />
<rect
y="181.15752"
x="164.50604"
height="7.4697757"
width="2.9879105"
id="rect4726"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 166,181.11199 0,-6.67727"
id="path4729"
inkscape:connector-curvature="0" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 165.9995,196.09707 0,-7.4494 10e-4,7.4494"
id="path4731"
inkscape:connector-curvature="0" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 163.01208,196.84405 2.98792,3.73489 0,3.73489"
id="path4733"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path4735"
d="m 164.50604,204.31383 2.98791,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 166,192.36218 29,0"
id="path4737"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="opacity:0.3;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path4739"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="matrix(0.42162733,0,0,0.42162733,119.62806,199.41032)" />
<text
sodipodi:linespacing="125%"
id="text4741"
y="192.36218"
x="145"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-style:normal;text-align:center;text-anchor:middle"
id="tspan4743"
y="192.36218"
x="145"
sodipodi:role="line">Multicast</tspan><tspan
style="font-style:normal;text-align:center;text-anchor:middle"
y="200.10144"
x="145"
sodipodi:role="line"
id="tspan4745">switches</tspan></text>
<path
transform="matrix(2,0,0,2,169.78516,77.804161)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path4747"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
</g>
</svg>
doc/hdlg/fig/ttl-inp.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="333.87131"
height="192"
id="svg4040"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="ttl-inp.svg">
<defs
id="defs4042">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path3992"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker4023"
style="overflow:visible">
<path
id="path4025"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM-9"
style="overflow:visible">
<path
id="path4441"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="5.6"
inkscape:cx="98.737814"
inkscape:cy="120.19381"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0">
<inkscape:grid
type="xygrid"
id="grid4556"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
originx="57.818153px"
originy="-829px" />
</sodipodi:namedview>
<metadata
id="metadata4045">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(57.818153,-31.362183)">
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 80,77.362183 108,0 0,10"
id="path5040"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccc" />
<rect
y="87.362183"
x="85"
height="75"
width="150"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:3, 1;stroke-dashoffset:0"
rx="5"
ry="5" />
<text
sodipodi:linespacing="125%"
id="text3769"
y="96.362183"
x="110"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="96.362183"
x="110"
sodipodi:role="line"
id="tspan4961"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4965">6x</tspan> input logic</tspan></text>
<path
style="opacity:0.3;fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 250,167.36218 c 5.16063,6.88084 5.16063,10.32125 0,17.20209 12.04146,0 20.64251,0 25.80315,-8.60104 -5.16064,-8.60105 -13.76169,-8.60105 -25.80315,-8.60105 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 235,132.36218 5.80315,0 0,38.60105 5,0"
id="path5544"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 235.80315,202.96323 5,0 0,-22 5,0"
id="path5546"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<g
id="g5231"
transform="translate(45.80315,0)">
<rect
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect5623"
width="80"
height="35"
x="105.15625"
y="183.44128" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="145"
y="197.36218"
id="text5625"
sodipodi:linespacing="125%"><tspan
id="tspan5627"
sodipodi:role="line"
x="145"
y="197.36218"
style="font-size:10px;text-align:center;text-anchor:middle">RS-485</tspan><tspan
sodipodi:role="line"
x="145"
y="209.86218"
style="font-size:10px;text-align:center;text-anchor:middle"
id="tspan5629">input logic</tspan></text>
</g>
<rect
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.30957046;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect2987"
width="4.3876133"
height="10.969033"
x="1.5074749"
y="134.68382" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 25.639338,123.71483 -38.391608,-3e-5"
id="path3767"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 3.701275,123.7148 0,10.96902"
id="path3769"
inkscape:connector-curvature="0" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 3.701275,145.65287 0,8.77521"
id="path3771"
inkscape:connector-curvature="0" />
<g
transform="matrix(0.61914096,0,0,0.61914096,13.573413,49.125415)"
id="g3783">
<path
inkscape:connector-curvature="0"
id="path3785"
d="m 141.73228,113.3858 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
transform="matrix(0.24999996,0,0,0.24999996,121.67006,91.240144)"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
sodipodi:ry="7.0866141"
sodipodi:rx="7.0866141"
sodipodi:cy="116.92912"
sodipodi:cx="159.44882"
id="path3787"
style="fill:none;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
</g>
<path
style="fill:none;stroke:#000000;stroke-width:0.30957049;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 184.04296,118.23031 0,28.51949 8.77523,-4.38762 0,-19.74425 -8.77523,-4.38762"
id="path3795"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:24.76563835px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="186.23677"
y="142.36218"
id="text3890"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3892"
x="186.23677"
y="142.36218"
style="font-size:6.19140959px">0</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3894"
y="127.00555"
x="186.23677"
style="font-size:24.76563835px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6.19140959px"
y="127.00555"
x="186.23677"
id="tspan3896"
sodipodi:role="line">1</tspan></text>
<rect
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect4288"
width="2.9879105"
height="7.4697757"
x="62.132988"
y="66.157524" />
<path
inkscape:connector-curvature="0"
id="path4290"
d="m 63.634008,66.111986 0,-6.677264"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path5106"
d="m 63.625728,81.097071 0,-7.449403 0.0013,7.449403"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path5108"
d="m 60.639029,81.844048 2.987913,3.734888 0,3.734888"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 62.132985,89.313824 2.987909,0"
id="path5110"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path5112"
d="m 63.626942,77.362183 16.373058,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="cc" />
<path
transform="matrix(0.42162733,0,0,0.42162733,17.255002,84.410317)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path5114"
style="opacity:0.3;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<path
inkscape:connector-curvature="0"
id="path3914"
d="m 35,112.36218 10,0"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path3916"
d="m 50,117.33122 5,0 0,-4.96904 5.484521,0 0,4.96904 9.515479,0"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cccccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 80,123.71481 21.32567,0"
id="path4051"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 91.453551,123.71481 0,17.55046 92.546449,2e-5"
id="path5191"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 114.4885,123.71481 69.5115,2e-5"
id="path4053"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 38.80218,123.71481 41.19782,0"
id="path4057"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#b2b2b2;fill-opacity:1;stroke:none;font-family:Sans"
x="-20"
y="97.362183"
id="text4203"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="-20"
y="97.362183"
style="font-style:normal;text-align:center;text-anchor:middle;fill:#b2b2b2;fill-opacity:1"
id="tspan5221">No sig.</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4209"
y="97.362183"
x="5.8950787"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-style:normal;text-align:center;text-anchor:middle"
y="97.362183"
x="5.8950791"
sodipodi:role="line"
id="tspan4217">Signal</tspan></text>
<path
transform="matrix(0.61914096,0,0,0.61914096,23.35841,134.06468)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path5193"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 1.507473,154.42808 4.387618,0"
id="path3773"
inkscape:connector-curvature="0" />
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.30957049;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 25.63934,119.32726 0,10.96899 10.96899,-6.58139 -10.96899,-6.58139 z"
id="path3757"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:2.00000858;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path3759"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.15478457,0,0,0.15478457,13.21805,105.61604)" />
<g
id="g3611"
transform="matrix(0.21125073,0,0,0.21125073,24.424795,78.429017)"
style="opacity:0.3;stroke:#000000;stroke-width:1.46541727;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none">
<path
transform="translate(-15.675442,33.433089)"
inkscape:connector-curvature="0"
id="path3607"
d="m 29.848669,186.25198 10.629922,0 3.543307,-10.62992 7.086614,0"
style="fill:none;stroke:#000000;stroke-width:1.46541727;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
style="fill:none;stroke:#000000;stroke-width:1.46541727;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 35.43307,209.05515 -10.629922,0 -3.543307,10.62992 -7.086614,0"
id="path3609"
inkscape:connector-curvature="0" />
</g>
<path
sodipodi:type="arc"
style="opacity:0.3;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path3126"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="matrix(0.61914096,0,0,0.61914096,-64.393851,134.06468)" />
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="M 80,32.362183 80,222.36218"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="matrix(2,0,0,2,54.78516,8.8041611)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5617"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="85"
y="47.362183"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="85"
y="47.362183"
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="47.362183"
x="75"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end;opacity:0.3"
y="47.362183"
x="75"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 192.94579,132.36575 42.05421,0"
id="path4955"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5020"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,54.78516,-37.195839)" />
<text
xml:space="preserve"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="50"
y="79.362183"
id="text5024"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="50"
y="79.362183"
id="tspan5026"
style="font-style:normal;text-align:center;text-anchor:middle">TTL</tspan><tspan
id="tspan5028"
sodipodi:role="line"
x="50"
y="87.101448"
style="font-style:normal;text-align:center;text-anchor:middle">switch</tspan></text>
<g
id="g5030"
transform="matrix(0.61914096,0,0,0.61914096,32.24774,2.7727728)"
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-opacity:1">
<path
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 141.73228,113.3858 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
id="path5032"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#b2b2b2;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5034"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.24999996,0,0,0.24999996,121.67006,91.240144)" />
</g>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 188,87.362183 0,32.999997"
id="path5038"
inkscape:connector-curvature="0" />
<g
id="g5291"
transform="matrix(0.51698617,0,0,0.51698617,-5.0338357,71.117635)">
<g
id="g5201"
transform="translate(0,3.8685751)">
<rect
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect4171"
width="48.357166"
height="38.685757"
x="309.55148"
y="114.596" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="334.74847"
y="130.44977"
id="text4181"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="334.74847"
y="130.44977"
style="font-size:11.60572624px;text-align:center;text-anchor:middle"
id="tspan4201">No sig.</tspan><tspan
id="tspan5930"
sodipodi:role="line"
x="334.74847"
y="144.95692"
style="font-size:11.60572624px;text-align:center;text-anchor:middle">detect</tspan></text>
</g>
</g>
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
d="m 35,102.36218 10,0"
id="path5207"
inkscape:connector-curvature="0" />
<path
sodipodi:nodetypes="cccccc"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 50,102.36218 5,0 0,4.96904 5.484521,0 0,-4.96904 9.515479,0"
id="path5209"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path5211"
d="m -20,107.33122 10,0"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path5213"
d="m -5,107.33122 5,0 0,-4.96904 5.484521,0 0,4.96904 9.515479,0"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cccccc" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
d="m -20,117.36218 10,0"
id="path5215"
inkscape:connector-curvature="0" />
<path
sodipodi:nodetypes="cccccc"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m -5,112.39314 5,0 0,4.96904 5.484521,0 0,-4.96904 9.515479,0"
id="path5217"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path5227"
d="m 115,117.36218 10,0"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path5229"
d="m 130,117.39314 5,0 0,-4.96904 5.48452,0 0,4.96904 9.51548,0"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cccccc" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
d="m 115,132.36218 10,0"
id="path5237"
inkscape:connector-curvature="0" />
<path
sodipodi:nodetypes="cccccc"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 130,137.36218 5,0 0,-4.96904 5.48452,0 0,4.96904 9.51548,0"
id="path5239"
inkscape:connector-curvature="0" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#b2b2b2;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none"
d="m 195,127.36218 10,0"
id="path5241"
inkscape:connector-curvature="0" />
<path
sodipodi:nodetypes="cccccc"
style="fill:none;stroke:#000000;stroke-width:0.61914092px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 210,127.39314 5,0 0,-4.96904 5.48452,0 0,4.96904 9.51548,0"
id="path5243"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="-45"
y="107.36218"
id="text3192"
sodipodi:linespacing="125%"><tspan
id="tspan3194"
sodipodi:role="line"
x="-45"
y="107.36218"
style="font-style:normal;text-align:center;text-anchor:middle">TTL</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3196"
y="117.36218"
x="-45"
style="font-size:6.19140959px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-style:normal;text-align:center;text-anchor:middle"
y="117.36218"
x="-45"
sodipodi:role="line"
id="tspan3198">TTL-BAR</tspan></text>
</g>
</svg>
doc/hdlg/fig/ttl-outp.svg 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="299.74023"
height="183"
id="svg3211"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="ttl-outp.svg">
<defs
id="defs3213">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="marker3062"
style="overflow:visible">
<path
id="path3064"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="4"
inkscape:cx="125.2271"
inkscape:cy="88.180609"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
showguides="true"
inkscape:guide-bbox="true">
<inkscape:grid
type="xygrid"
id="grid3236"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
spacingx="1px"
spacingy="1px"
originx="85.5px"
originy="-709px" />
</sodipodi:namedview>
<metadata
id="metadata3216">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(85.5,-160.36218)">
<rect
y="212.36218"
x="10"
height="85"
width="125"
id="rect3779"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:3, 1;stroke-dashoffset:0"
rx="5"
ry="5" />
<path
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:none"
d="m 147.81815,161.36218 0,181"
id="path4728"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="142.5"
y="176.36218"
id="text4947"
sodipodi:linespacing="125%"><tspan
id="tspan4949"
sodipodi:role="line"
x="142.5"
y="176.36218"
style="font-size:14px;font-weight:bold;text-align:end;text-anchor:end">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4951"
y="176.36218"
x="152.5"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;text-align:start;text-anchor:start;opacity:0.3"
y="176.36218"
x="152.5"
sodipodi:role="line"
id="tspan4953">Board</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4484"
y="256.36218"
x="182.5"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan4488"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
y="256.36218"
x="182.5"
sodipodi:role="line">TTL output</tspan><tspan
style="font-size:6px;font-weight:normal;text-align:center;text-anchor:middle"
y="263.86218"
x="182.5"
sodipodi:role="line"
id="tspan4342">(front panel)</tspan></text>
<path
inkscape:connector-curvature="0"
id="path4496"
d="m 140,257.36218 18,0"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
sodipodi:nodetypes="cc" />
<path
transform="matrix(2,0,0,2,122.78516,142.80416)"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
sodipodi:ry="1"
sodipodi:rx="1"
sodipodi:cy="57.279011"
sodipodi:cx="12.60742"
id="path5613"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:type="arc" />
<path
inkscape:connector-curvature="0"
id="path5329"
d="m 107.83465,232.55904 0,46.063 14.17323,-7.08662 0,-31.88976 -14.17323,-7.08662"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text5331"
y="271.5354"
x="111.37795"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px"
y="271.5354"
x="111.37795"
id="tspan5333"
sodipodi:role="line">0</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="111.37795"
y="247.36218"
id="text5335"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan5337"
x="111.37795"
y="247.36218"
style="font-size:10px">1</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 65,271.22043 5.629914,0 0,5.37004 8.85827,0 0,-5.37004 10.511816,0"
id="path5345"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccccc" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path5349"
d="m 24.566924,243.36218 83.433076,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path5357"
d="m 24.566934,243.36218 0,24.62993 83.267716,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="ccc" />
<g
id="g5367"
transform="translate(-561.85039,119.17318)">
<path
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 602.36221,141.73229 0,17.71654 17.71654,-10.62992 -17.71654,-10.62992 z"
id="path5323"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:2.00000024;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path5325"
sodipodi:cx="159.44882"
sodipodi:cy="116.92912"
sodipodi:rx="7.0866141"
sodipodi:ry="7.0866141"
d="m 166.53544,116.92912 c 0,3.91383 -3.17279,7.08662 -7.08662,7.08662 -3.91383,0 -7.08661,-3.17279 -7.08661,-7.08662 0,-3.91383 3.17278,-7.08661 7.08661,-7.08661 3.91383,0 7.08662,3.17278 7.08662,7.08661 z"
transform="matrix(0.24999996,0,0,0.24999996,581.98819,119.58663)" />
</g>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 122.00788,257.36218 12.99212,0"
id="path5373"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="translate(-85.4163,274.07868)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path5375"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<path
sodipodi:nodetypes="cccccc"
inkscape:connector-curvature="0"
id="path4089"
d="m 65,236.22043 5.629914,0 0,-5.37004 8.85827,0 0,5.37004 10.511816,0"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4091"
d="m 10,257.36218 14,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m -20,257.36218 25,0"
id="path4313"
inkscape:connector-curvature="0" />
<rect
y="187.36218"
x="-85"
height="155"
width="60"
id="rect4950"
style="opacity:0.3;fill:#e5e5e5;fill-opacity:1;stroke-width:0.56;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0" />
<path
inkscape:connector-curvature="0"
id="path4952"
d="m -85,187.36218 60,0 0,155"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="ccc" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="-30"
y="260.36218"
id="text4969"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4971"
x="-30"
y="260.36218"
style="text-align:end;text-anchor:end">pulse_o</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4973"
y="202.36218"
x="-27.705078"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="202.36218"
x="-27.705078"
id="tspan4975"
sodipodi:role="line"
style="font-weight:bold;text-align:end;text-anchor:end">Conv.</tspan><tspan
y="214.86218"
x="-27.705078"
sodipodi:role="line"
id="tspan4977"
style="font-weight:bold;text-align:end;text-anchor:end">common</tspan><tspan
y="227.36218"
x="-27.705078"
sodipodi:role="line"
id="tspan4979"
style="font-weight:bold;text-align:end;text-anchor:end">gateware</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.3;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="190"
y="322.36218"
id="text4336"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="190"
y="322.36218"
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4338">RS-485 output</tspan><tspan
sodipodi:role="line"
x="190"
y="329.86218"
style="font-size:6px;font-weight:normal;text-align:center;text-anchor:middle"
id="tspan4340">(rear panel)</tspan></text>
<path
sodipodi:nodetypes="ccc"
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker3062)"
d="m -5,257.36218 0,65 163,0"
id="path4344"
inkscape:connector-curvature="0" />
<path
sodipodi:type="arc"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.25;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="path4348"
sodipodi:cx="12.60742"
sodipodi:cy="57.279011"
sodipodi:rx="1"
sodipodi:ry="1"
d="m 13.60742,57.279011 c 0,0.552285 -0.447715,1 -1,1 -0.552285,0 -1,-0.447715 -1,-1 0,-0.552285 0.447715,-1 1,-1 0.552285,0 1,0.447715 1,1 z"
transform="matrix(2,0,0,2,122.78516,207.80416)" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 115,236.36218 0,-18 -6,0"
id="path4350"
inkscape:connector-curvature="0" />
<text
sodipodi:linespacing="125%"
id="text4352"
y="220.36218"
x="108"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:end;text-anchor:end"
y="220.36218"
x="108"
id="tspan4354"
sodipodi:role="line">TTL switch (active-high)</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3769"
y="292.36218"
x="110"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px;text-align:center;text-anchor:middle"
y="292.36218"
x="110"
sodipodi:role="line"
id="tspan4961"><tspan
style="font-size:6px;font-weight:bold;text-align:center;text-anchor:middle"
id="tspan4965">6x</tspan> output logic</tspan></text>
<path
style="opacity:0.3;fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m -19.488184,247.73222 5.629914,0 0,-5.37004 8.85827,0 0,5.37004 10.511816,0"
id="path4424"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccccc" />
</g>
</svg>
doc/hdlg/hdlg-conv-ttl-rs485.bib 0 → 100644
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@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{conv-ttl-rs485-ohwr,
title = {{CONV-TTL-RS485 Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{conv-ttl-rs485-ug,
title = {{CONV-TTL-RS485 User Guide on OHWR}},
howpublished = {\url{http://www.ohwr.org/documents/351}}
}
@misc{conv-ttl-rs485-sch,
title = {{CONV-TTL-RS485 on CERN EDMS}}},
howpublished = {\url{https://edms.cern.ch/nav/P:EDA-02541:V0/I:EDA-02541-V1-0:V0/TAB4}}
}
@article{rs485-fs,
title = {Detection of {RS}-485 signal loss},
url = {http://www.tij.co.jp/jp/lit/an/slyt257/slyt257.pdf},
number = {4Q},
urldate = {2014-08-06},
journal = {Texas instruments Appl. Note Literature},
author = {Gingerich, Kevin},
year = {2006},
file = {Detection of RS-485 signal loss - slyt257.pdf:/home/tstana/.mozilla/firefox/ao4zesfb.default/zotero/storage/4SHSRX25/slyt257.pdf:application/pdf}
}
@misc{conv-common-gw,
title = {{Converter board common gateware specification on OHWR}},
howpublished = {\url{http://www.ohwr.org/documents/352}}
}
doc/hdlg/hdlg-conv-ttl-rs485.tex 0 → 100644
View file @ 3395277e
%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline{toc}{section}{Revision history}
\section*{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
06-08-2014 & 0.1 & First draft \\
12-08-2014 & 0.2 & Release for gateware v0.0 \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% List of figs, tables
%------------------------------------------------------------------------------
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\listoffigures
%\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
LSR & Line Status Register \\
MSWR & Multicast Switch Register \\
SR & Status Register \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document is the HDL guide for the CONV-TTL-RS485 project~\cite{conv-ttl-rs485-ohwr}.
The HDL for the CONV-TTL-RS485 board uses the converter board common gateware~\cite{conv-common-gw}
as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-RS485.
This short HDL guide explains these peculiarities and the corresponding logic implemented.
\subsection{Additional documentation}
\begin{itemize}
\item Converter board common gateware~\cite{conv-common-gw}
\item CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}
\item CONV-TTL-RS485 schematics~\cite{conv-ttl-rs485-sch}
\item CONV-TTL-RS485 OHWR Wiki page~\cite{conv-ttl-rs485-ohwr}
\end{itemize}
%==============================================================================
% SEC: Overview
%==============================================================================
\section{Overview}
\label{sec:overview}
A block diagram of the HDL is shown in Figure~\ref{fig:block-diagram}. This document
will detail each of the blocks in the following sections. For a more
general look at the pulse repetition logic, refer to the CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of CONV-TTL-RS485 gateware}
\end{figure}
\pagebreak
\section{Input logic}
%==============================================================================
% SEC: TTL input logic
%==============================================================================
\subsection{TTL/TTL-BAR input logic}
\label{sec:ttl-input}
The TTL/TTL-BAR input logic is shown in Figure~\ref{fig:ttl-inp}. It assures
an active-high pulse to the \textit{pulse\_i} input of the \textit{conv\_common\_gw}
component and adapts for TTL-BAR pulses that may be input when the TTL switch is
on.
In addition, because in TTL-BAR mode a lack of signal on the line is high (due
to the on-board Schmitt-trigger buffer), the \textit{no signal detect} block
(Figure~\ref{fig:no-sig-detect}) disables this line if it is high for 100~${\mu}s$,
to allow propagation of RS-485 pulses arriving on the rear panel while the channel
has no cable plugged in while in TTL-BAR mode.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/ttl-inp}}
\caption{\label{fig:ttl-inp} TTL/TTL-BAR input logic}
\centerline{\includegraphics[width=.8\textwidth]{fig/no-sig-detect}}
\caption{\label{fig:no-sig-detect} No signal detect block}
\end{figure}
%==============================================================================
% SEC: RS-485 input logic
%==============================================================================
\subsection{RS-485 input logic}
\label{sec:rs485-input}
A simplified diagram of the RS-485 input logic is shown in Figure~\ref{fig:rs485-inp}.
The actual logic is active-low logic, due to the Schmitt trigger inverters on the
signals from the RS-485 and failsafe transceiver chips. The RS-485 trigger is only propagated to
\textit{conv\_common\_gw} if a cable is plugged in, indicated by the signal loss detection
mechanism~\cite{rs485-fs}. The AND gate in the mechanism is implemented internally to the FPGA and it is this gate that
enables RS-485 trigger propagation.
The failsafe lines are reflected in the LSR register (see the memory map in the
CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}), as shown in the figure.
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/rs485-inp}}
\caption{\label{fig:rs485-inp} Simplified diagram of RS-485 logic}
\end{figure}
%==============================================================================
% SEC: First pulse inhibit
%==============================================================================
\subsection{First pulse inhibit mechanism}
\label{sec:first-pulse-inhibit}
The first pulse inhibit mechanism (Figure~\ref{fig:first-pulse-inhibit}) is implemented
in the form of a counter which waits for 100~${\mu}s$ after reset prior to enabling the
line. It is implemented because in TTL-BAR mode, until an inactive line is disabled,
the TTL line is high and this may lead to a pulse triggered on the channel, due to reset
of modules within the \textit{conv\_common\_gw} component.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/first-pulse-inhibit}}
\caption{\label{fig:first-pulse-inhibit} First pulse inhibit mechanism}
\end{figure}
By keeping the line disabled until the no signal detect block in the TTL input logic
(Section~\ref{sec:ttl-input}) disables the line, no pulse is triggered on the channel.
To keep the logic simple, the pulse inhibit logic disables the line even when the board is in
TTL repetition mode. Since in practice the effect it has on the input to the
\textit{conv\_common\_gw} is extending the 100~ms reset by 100~${\mu}s$, an extra
0.1\% delay from reset to full pulse replication capabilities is deemed insignificant
in comparison to logic simplification.
%==============================================================================
% SEC: Line input logic
%==============================================================================
\subsection{Line input logic}
\label{sec:line-input}
Since the TTL and RS-485 lines are passed through Schmitt trigger inverters
prior to being input to the FPGA, they are active-low. The line input logic
(Figure~\ref{fig:line-inp}) adapts this to active-high logic prior to inputting
them to the LSR, so that the state of the line at the input of the board (before
the Schmitt trigger) is reflected in the LSR.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/line-inp}}
\caption{\label{fig:line-inp} Line input logic}
\end{figure}
%==============================================================================
% SEC: Switch input logic
%==============================================================================
\subsection{Switch input logic}
\label{sec:sw-input}
Similar to the line input logic (Section~\ref{sec:line-input}), the switch
lines must be negated for their active-high reflection in the SR and MSWR, as
shown in Figure~\ref{fig:switches}.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth]{fig/switches}}
\caption{\label{fig:switches} Switch input logic}
\end{figure}
\pagebreak
\section{Output logic}
%==============================================================================
% SEC: TTL/TTL-BAR output logic
%==============================================================================
\subsection{TTL/TTL-BAR output logic}
\label{sec:ttl-output}
The TTL/TTL-BAR output logic (Figure~\ref{fig:ttl-outp}) ensures that TTL pulses
are propagated from the \textit{pulse\_o} output of \textit{conv\_common\_o} to
the FPGA output when the TTL switch is ON, or that TTL-BAR pulses are propagated
when it is OFF.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/ttl-outp}}
\caption{\label{fig:ttl-outp} TTL output logic}
\end{figure}
%==============================================================================
% SEC: Pulse LED logic
%==============================================================================
\subsection{Pulse LED output logic}
\label{sec:pulse-led}
Since in the CONV-TTL-RS485 schematics the pulse LEDs are driven from inverting
Schmitt triggers to ground, the active-high pulse LED output from \textit{conv\_common\_gw}
must be inverted prior to driving the Schmitt trigger. This is done via the pulse
LED logic (Figure~\ref{fig:pulse-led}).
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/pulse-led}}
\caption{\label{fig:pulse-led} Pulse LED logic}
\end{figure}
%==============================================================================
% SEC: Bicolor LED logic
%==============================================================================
\subsection{Bicolor LED output logic}
\label{sec:bicolor-led}
The bicolor LED logic external to the \textit{conv\_common\_gw} takes the
bicolor LED outputs as well as specific control pins (such as, for example,
the I$^2$C LED drive pin, flashing four times on an I$^2$C transfer) and connects
them to the bicolor LEDs, adding multiplexer logic where needed to control the lighting
and color of the LED.
The way in which each LED is turned on is described in the CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}.
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hdlg-conv-ttl-rs485}
\addcontentsline{toc}{section}{References}
\end{document}
conv-common-gw @ 3ae0cfc2
Subproject commit 3ae0cfc27599e426d1eeb47bb4312a88a4aff160
syn/Golden/Makefile 0 → 100644
View file @ 3395277e
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_rs485.xise
ISE_CRAP := *.b conv_ttl_rs485_summary.html *.tcl conv_ttl_rs485.bld conv_ttl_rs485.cmd_log *.drc conv_ttl_rs485.lso *.ncd conv_ttl_rs485.ngc conv_ttl_rs485.ngd conv_ttl_rs485.ngr conv_ttl_rs485.pad conv_ttl_rs485.par conv_ttl_rs485.pcf conv_ttl_rs485.prj conv_ttl_rs485.ptwx conv_ttl_rs485.stx conv_ttl_rs485.syr conv_ttl_rs485.twr conv_ttl_rs485.twx conv_ttl_rs485.gise conv_ttl_rs485.unroutes conv_ttl_rs485.ut conv_ttl_rs485.xpi conv_ttl_rs485.xst conv_ttl_rs485_bitgen.xwbt conv_ttl_rs485_envsettings.html conv_ttl_rs485_guide.ncd conv_ttl_rs485_map.map conv_ttl_rs485_map.mrp conv_ttl_rs485_map.ncd conv_ttl_rs485_map.ngm conv_ttl_rs485_map.xrpt conv_ttl_rs485_ngdbuild.xrpt conv_ttl_rs485_pad.csv conv_ttl_rs485_pad.txt conv_ttl_rs485_par.xrpt conv_ttl_rs485_summary.xml conv_ttl_rs485_usage.xml conv_ttl_rs485_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
syn/Golden/Manifest.py 0 → 100644
View file @ 3395277e
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_rs485"
syn_project = "conv_ttl_rs485.xise"
modules = {
"local" : [
"../../top"
]
}
syn/Golden/conv_ttl_rs485.xise 0 → 100644
View file @ 3395277e
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x0b000044" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-24T16:52:24" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B340E1CEFABAF7AEA6E4A2576F7AC596" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../../top/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../top/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
syn/Release/Makefile 0 → 100644
View file @ 3395277e
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_rs485.xise
ISE_CRAP := *.b conv_ttl_rs485_summary.html *.tcl conv_ttl_rs485.bld conv_ttl_rs485.cmd_log *.drc conv_ttl_rs485.lso *.ncd conv_ttl_rs485.ngc conv_ttl_rs485.ngd conv_ttl_rs485.ngr conv_ttl_rs485.pad conv_ttl_rs485.par conv_ttl_rs485.pcf conv_ttl_rs485.prj conv_ttl_rs485.ptwx conv_ttl_rs485.stx conv_ttl_rs485.syr conv_ttl_rs485.twr conv_ttl_rs485.twx conv_ttl_rs485.gise conv_ttl_rs485.unroutes conv_ttl_rs485.ut conv_ttl_rs485.xpi conv_ttl_rs485.xst conv_ttl_rs485_bitgen.xwbt conv_ttl_rs485_envsettings.html conv_ttl_rs485_guide.ncd conv_ttl_rs485_map.map conv_ttl_rs485_map.mrp conv_ttl_rs485_map.ncd conv_ttl_rs485_map.ngm conv_ttl_rs485_map.xrpt conv_ttl_rs485_ngdbuild.xrpt conv_ttl_rs485_pad.csv conv_ttl_rs485_pad.txt conv_ttl_rs485_par.xrpt conv_ttl_rs485_summary.xml conv_ttl_rs485_usage.xml conv_ttl_rs485_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
syn/Release/Manifest.py 0 → 100644
View file @ 3395277e
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_rs485"
syn_project = "conv_ttl_rs485.xise"
modules = {
"local" : [
"../../top"
]
}
syn/Release/conv_ttl_rs485.xise 0 → 100644
View file @ 3395277e
<?xml version="1.0" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;&gt;" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x0b000044" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-24T16:52:24" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B340E1CEFABAF7AEA6E4A2576F7AC596" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../../top/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../top/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
top/Manifest.py 0 → 100644
View file @ 3395277e
files = [
"conv_ttl_rs485.ucf",
"conv_ttl_rs485.vhd"
]
modules = {
"local" : [
"../ip_cores/conv-common-gw"
],
}
top/conv_ttl_rs485.ucf 0 → 100644
View file @ 3395277e
#==============================================================================
# CERN (BE-CO-HT)
# UCF defintions file for CONV-TTL-RS485 gateware
#==============================================================================
#
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2014-07-24
#
# version: 1.0
#
# description:
# This file contains the pin definitions for the CONV-TTL-RS485 FPGA.
#
# references:
# [1] CONV-TTL-RS485 schematics from latest version of project at:
# https://edms.cern.ch/nav/EDA-02541
#
#==============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#==============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#==============================================================================
# last changes:
# 2014-07-24 Theodor Stana t.stana@cern.ch File created
#==============================================================================
# TODO: -
#==============================================================================
#=============================================================================
# CLOCKS
#=============================================================================
NET "clk_20_i" LOC = E16;
NET "clk_20_i" TNM_NET = "clk_20";
TIMESPEC TSCLK20 = PERIOD "clk_20" 20 MHz HIGH 50 %;
NET "clk_125_p_i" LOC = H12;
NET "clk_125_n_i" LOC = G11;
NET "clk_125_p_i" TNM_NET = "clk_125";
TIMESPEC TSCLK125 = PERIOD "clk_125" 125 MHz HIGH 50 %;
#==============================================================================
# FRONT PANEL
#==============================================================================
#-----------------------------------------------------------------------------
# TTL I/O
#-----------------------------------------------------------------------------
NET "ttl_n_i[0]" LOC = T3;
NET "ttl_n_i[0]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[1]" LOC = U4;
NET "ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[2]" LOC = W3;
NET "ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[3]" LOC = W4;
NET "ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[4]" LOC = V3;
NET "ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[5]" LOC = U3;
NET "ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "ttl_o[0]" LOC = D1;
NET "ttl_o[0]" IOSTANDARD = LVCMOS33;
NET "ttl_o[1]" LOC = E1;
NET "ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "ttl_o[2]" LOC = F2;
NET "ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "ttl_o[3]" LOC = F1;
NET "ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "ttl_o[4]" LOC = G1;
NET "ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "ttl_o[5]" LOC = H2;
NET "ttl_o[5]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# INV-TTL I/O
#-----------------------------------------------------------------------------
NET "inv_n_i[0]" LOC = Y1;
NET "inv_n_i[0]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[1]" LOC = Y2;
NET "inv_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[2]" LOC = AA1;
NET "inv_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[3]" LOC = AA2;
NET "inv_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_o[0]" LOC = H1;
NET "inv_o[0]" IOSTANDARD = LVCMOS33;
NET "inv_o[1]" LOC = J1;
NET "inv_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_o[2]" LOC = K2;
NET "inv_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_o[3]" LOC = K1;
NET "inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_front_o[0]" LOC = H3;
NET "led_front_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_o[1]" LOC = J4;
NET "led_front_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_o[2]" LOC = J3;
NET "led_front_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_o[3]" LOC = K3;
NET "led_front_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_o[4]" LOC = L4;
NET "led_front_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_o[5]" LOC = L3;
NET "led_front_o[5]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[0]" LOC = AA4;
NET "led_inv_o[0]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[1]" LOC = AB4;
NET "led_inv_o[1]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[2]" LOC = AB5;
NET "led_inv_o[2]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[3]" LOC = Y5;
NET "led_inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Status LEDs
#------------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M5;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = M4;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = K6;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = K5;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_gp_2_4_o" LOC = F9;
NET "led_gp_2_4_o" IOSTANDARD = LVCMOS33;
NET "led_gp_1_3_o" LOC = F10;
NET "led_gp_1_3_o" IOSTANDARD = LVCMOS33;
NET "led_oterm_wr_o" LOC = E5;
NET "led_oterm_wr_o" IOSTANDARD = LVCMOS33;
NET "led_iterm_syserror_o" LOC = F7;
NET "led_iterm_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_gf_syspw_o" LOC = F8;
NET "led_gf_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_ttl_i2c_o" LOC = E6;
NET "led_ttl_i2c_o" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
#=============================================================================
#-----------------------------------------------------------------------------
# RS-485 I/O (fs = failsafe)
#-----------------------------------------------------------------------------
NET "rs485_n_i[0]" LOC = Y12;
NET "rs485_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[1]" LOC = AB12;
NET "rs485_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[2]" LOC = AB11;
NET "rs485_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[3]" LOC = AB10;
NET "rs485_n_i[3]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[4]" LOC = AB9;
NET "rs485_n_i[4]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[5]" LOC = AA8;
NET "rs485_n_i[5]" IOSTANDARD = LVCMOS33;
NET "rs485_o[0]" LOC = W18;
NET "rs485_o[0]" IOSTANDARD = LVCMOS33;
NET "rs485_o[1]" LOC = Y18;
NET "rs485_o[1]" IOSTANDARD = LVCMOS33;
NET "rs485_o[2]" LOC = W17;
NET "rs485_o[2]" IOSTANDARD = LVCMOS33;
NET "rs485_o[3]" LOC = Y17;
NET "rs485_o[3]" IOSTANDARD = LVCMOS33;
NET "rs485_o[4]" LOC = Y16;
NET "rs485_o[4]" IOSTANDARD = LVCMOS33;
NET "rs485_o[5]" LOC = Y15;
NET "rs485_o[5]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[0]" LOC = AA12;
NET "rs485_fs_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[1]" LOC = Y11;
NET "rs485_fs_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[2]" LOC = Y10;
NET "rs485_fs_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[3]" LOC = AA10;
NET "rs485_fs_n_i[3]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[4]" LOC = AB8;
NET "rs485_fs_n_i[4]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[5]" LOC = AB7;
NET "rs485_fs_n_i[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Input and output termination enable lines
#------------------------------------------------------------------------------
NET "iterm_en_o[0]" LOC = W14;
NET "iterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[1]" LOC = W13;
NET "iterm_en_o[1]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[2]" LOC = W12;
NET "iterm_en_o[2]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[3]" LOC = W11;
NET "iterm_en_o[3]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[4]" LOC = W10;
NET "iterm_en_o[4]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[5]" LOC = W9;
NET "iterm_en_o[5]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[0]" LOC = T22;
NET "oterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[1]" LOC = T21;
NET "oterm_en_o[1]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[2]" LOC = T20;
NET "oterm_en_o[2]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[3]" LOC = U20;
NET "oterm_en_o[3]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[4]" LOC = V20;
NET "oterm_en_o[4]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[5]" LOC = W20;
NET "oterm_en_o[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_rear_n_o[0]" LOC = AB17;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[1]" LOC = AB19;
NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[2]" LOC = AA16;
NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[3]" LOC = AA18;
NET "led_rear_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[4]" LOC = AB16;
NET "led_rear_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[5]" LOC = AB18;
NET "led_rear_n_o[5]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Channel enable signals
#=============================================================================
NET "global_oen_o" LOC = N3;
NET "global_oen_o" IOSTANDARD = LVCMOS33;
NET "ttl_oen_o" LOC = M3;
NET "ttl_oen_o" IOSTANDARD = LVCMOS33;
NET "inv_oen_o" LOC = N4;
NET "inv_oen_o" IOSTANDARD = LVCMOS33;
NET "rs485_oen_o" LOC = AB6;
NET "rs485_oen_o" IOSTANDARD = LVCMOS33;
#=============================================================================
# VME CONNECTOR SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# I2C lines
#-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_en_o" LOC = H18;
NET "scl_en_o" IOSTANDARD = LVCMOS33;
NET "scl_en_o" DRIVE = 4;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
NET "sda_en_o" LOC = J19;
NET "sda_en_o" IOSTANDARD = LVCMOS33;
NET "sda_en_o" SLEW = FAST;
NET "sda_en_o" DRIVE = 4;
#-----------------------------------------------------------------------------
# System reset line
#-----------------------------------------------------------------------------
NET "vme_sysreset_n_i" LOC = L20;
NET "vme_sysreset_n_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Geographical addressing lines
#-----------------------------------------------------------------------------
NET "vme_gap_i" LOC = H19;
NET "vme_gap_i" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[0]" LOC = H20;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" LOC = J20;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" LOC = K19;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" LOC = K20;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" LOC = L19;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
#=============================================================================
# WHITE RABBIT
#=============================================================================
#-----------------------------------------------------------------------------
# DAC control
#-----------------------------------------------------------------------------
NET "dac20_sclk_o" LOC = Y13;
NET "dac20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac20_din_o" LOC = AB13;
NET "dac20_din_o" IOSTANDARD = LVCMOS33;
NET "dac20_sync_n_o" LOC = AB14;
NET "dac20_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac125_sclk_o" LOC = AA14;
NET "dac125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac125_din_o" LOC = Y14;
NET "dac125_din_o" IOSTANDARD = LVCMOS33;
NET "dac125_sync_n_o" LOC = AB15;
NET "dac125_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# SFP connection
#-----------------------------------------------------------------------------
NET "sfp_los_i" LOC = G3;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_present_i" LOC = G4;
NET "sfp_present_i" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_o" LOC = C4;
NET "sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "sfp_scl_b" LOC = F3;
NET "sfp_scl_b" IOSTANDARD = LVCMOS33;
NET "sfp_sda_b" LOC = E3;
NET "sfp_sda_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = E4;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = D2;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#=============================================================================
# OTHER SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# One-wire thermometer data signal
#-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# General-purpose switches
#-----------------------------------------------------------------------------
NET "sw_gp_n_i[0]" LOC = F22;
NET "sw_gp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[1]" LOC = G22;
NET "sw_gp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[2]" LOC = H21;
NET "sw_gp_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[3]" LOC = H22;
NET "sw_gp_n_i[3]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[4]" LOC = J22;
NET "sw_gp_n_i[4]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[5]" LOC = K21;
NET "sw_gp_n_i[5]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[6]" LOC = K22;
NET "sw_gp_n_i[6]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[7]" LOC = L22;
NET "sw_gp_n_i[7]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Multicast switches
#-----------------------------------------------------------------------------
NET "sw_multicast_n_i[0]" LOC = D21;
NET "sw_multicast_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[1]" LOC = C22;
NET "sw_multicast_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[2]" LOC = B22;
NET "sw_multicast_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[3]" LOC = B21;
NET "sw_multicast_n_i[3]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# RTM detection lines
#-----------------------------------------------------------------------------
NET "rtmm_i[0]" LOC = V21;
NET "rtmm_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[1]" LOC = V22;
NET "rtmm_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[2]" LOC = U22;
NET "rtmm_i[2]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[0]" LOC = W22;
NET "rtmp_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[1]" LOC = Y22;
NET "rtmp_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[2]" LOC = Y21;
NET "rtmp_i[2]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Flash memory
#-----------------------------------------------------------------------------
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = LVCMOS33;
NET "flash_cs_n_o" LOC = AA3;
NET "flash_cs_n_o" IOSTANDARD = LVCMOS33;
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = LVCMOS33;
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = LVCMOS33;
top/conv_ttl_rs485.vhd 0 → 100644
View file @ 3395277e
--==============================================================================
-- CERN (BE-CO-HT)
-- Top-level design for CONV-TTL-RS485
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-07-24
--
-- version: 1.0
--
-- description:
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-07-24 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
rs485_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i : in std_logic_vector(5 downto 0);
rs485_fs_n_i : in std_logic_vector(5 downto 0);
rs485_o : out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o : out std_logic_vector(5 downto 0);
oterm_en_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_o : out std_logic_vector(5 downto 0);
led_inv_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_scl_b : inout std_logic;
sfp_sda_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_gp_2_4_o : out std_logic;
led_gp_1_3_o : out std_logic;
led_oterm_wr_o : out std_logic;
led_iterm_syserror_o : out std_logic;
led_gf_syspw_o : out std_logic;
led_ttl_i2c_o : out std_logic
);
end entity conv_ttl_rs485;
architecture arch of conv_ttl_rs485 is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of repetition channels
constant c_nr_chans : integer := 6;
constant c_nr_inv_chans : integer := 4;
-- Number of bicolor LED lines & columns
constant c_bicolor_led_lines : integer := 2;
constant c_bicolor_led_cols : integer := 6;
-- Board ID - ASCII string "T485"
constant c_board_id : std_logic_vector(31 downto 0) := x"54343835";
-- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"00";
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (c_nr_chans-1 downto 0) of unsigned(10 downto 0);
type t_led_inv_cnt is array(c_nr_chans-1 downto 0) of unsigned(18 downto 0);
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signal
signal rst_20_n : std_logic;
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_in : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_out : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_rs485 : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0);
-- Line signals -- for reflection in line status register of conv_common_gw
signal line_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal line_invttl : std_logic_vector(3 downto 0);
signal line_rs485 : std_logic_vector(c_nr_chans-1 downto 0);
-- Switch signals (for inverting switch inputs to the common g/w)
signal sw_ttl : std_logic;
signal sw_iterm_en : std_logic;
signal sw_oterm_en : std_logic;
signal sw_gp : std_logic_vector(7 downto 0);
signal sw_other : std_logic_vector(31 downto 0);
-- No signal on TTL-BAR
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig : std_logic_vector(c_nr_chans-1 downto 0);
-- INV-TTL internal signals
signal inv_n : std_logic_vector(3 downto 0);
signal inv_n_d0 : std_logic_vector(3 downto 0);
signal inv_n_fedge_p : std_logic_vector(3 downto 0);
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
signal led_i2c : std_logic;
signal led_i2c_err : std_logic;
signal led_inv : std_logic_vector(3 downto 0);
signal led_inv_cnt : t_led_inv_cnt;
-- System error (ERR) LED control
signal led_syserr : std_logic;
-- Bicolor LED signals
signal bicolor_led_state : std_logic_vector(2*c_bicolor_led_cols*c_bicolor_led_lines-1 downto 0);
signal bicolor_led_col : std_logic_vector(c_bicolor_led_cols-1 downto 0);
signal bicolor_led_line : std_logic_vector(c_bicolor_led_lines-1 downto 0);
signal bicolor_led_line_oen : std_logic_vector(c_bicolor_led_lines-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Channel input logic
--============================================================================
-- TTL switch
sw_ttl <= not sw_gp_n_i(7);
-- The "no signal detect" block
--
-- If the signal line is high for 100 us, the ttlbar_nosig lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to c_nr_chans-1 loop
if (rst_20_n = '0') or (ttl_n_i(i) = '0') then
ttlbar_nosig(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (sw_ttl = '0') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 1999) then
ttlbar_nosig(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end loop;
end if;
end process p_ttlbar_nosig;
-- TTL and blocking inputs
pulse_ttl <= not ttl_n_i when sw_ttl = '1' else
ttl_n_i and (not ttlbar_nosig);
-- Pulse input on RS-485 side valid only when failsafe not high
-- see Texas slyt257 for implementation details
gen_rs485_input : for i in 0 to c_nr_chans-1 generate
rs485_fs(i) <= rs485_n_i(i) nor rs485_fs_n_i(i);
pulse_rs485(i) <= (not rs485_n_i(i)) when rs485_fs(i) = '0' else
'0';
end generate gen_rs485_input;
-- This process has the effect of extending the reset an extra 100 us, to avoid
-- a pulse being generated or erroneously counted during the period of no signal
-- detect
p_inhibit_first_pulse : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inhibit_cnt <= (others => '0');
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then
inhibit_first_pulse <= '0';
end if;
end if;
end if;
end process p_inhibit_first_pulse;
-- Delay inhibit first pulse signal, use this to enable input, thus avoiding
-- internal reset states of conv_common_gw
p_inhibit_first_pulse_d0 : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inhibit_first_pulse_d0 <= '1';
else
inhibit_first_pulse_d0 <= inhibit_first_pulse;
end if;
end if;
end process;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_rs485) when (inhibit_first_pulse = '0') else
(others => '0');
-- Line inputs for reflection in status register
line_ttl <= not ttl_n_i;
line_invttl <= not inv_n_i;
line_rs485 <= not rs485_n_i;
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
sw_other( 3 downto 0) <= not sw_multicast_n_i;
sw_other(31 downto 4) <= (others => '0');
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
cmp_conv_common : conv_common_gw
generic map
(
-- Number of repeater channels
g_nr_chans => c_nr_chans,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => false,
g_pgen_gf_len => 1,
--g_with_pulse_cnt => true,
--g_with_pulse_timetag => true,
--g_with_man_trig => true,
--g_man_trig_pwidth => 24,
--g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
port map
(
-- Clocks
clk_20_i => clk_20_i,
clk_125_p_i => clk_125_p_i,
clk_125_n_i => clk_125_n_i,
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o => rst_20_n,
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Channel enable
global_ch_oen_o => global_oen_o,
pulse_front_oen_o => ttl_oen_o,
pulse_rear_oen_o => rs485_oen_o,
inv_oen_o => inv_oen_o,
-- Front panel channels
pulse_i => pulse_in,
pulse_o => pulse_out,
-- Channel leds
led_pulse_o => led_pulse,
-- I2C interface
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- VME interface
vme_sysreset_n_i => vme_sysreset_n_i,
vme_ga_i => vme_ga_i,
vme_gap_i => vme_gap_i,
-- SPI interface to on-board flash chip
flash_cs_n_o => flash_cs_n_o,
flash_sclk_o => flash_sclk_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o => dac20_din_o,
dac20_sclk_o => dac20_sclk_o,
dac20_sync_n_o => dac20_sync_n_o,
-- 125 MHz clock generator control
dac125_din_o => dac125_din_o,
dac125_sclk_o => dac125_sclk_o,
dac125_sync_n_o => dac125_sync_n_o,
-- SFP lines
sfp_los_i => sfp_los_i,
sfp_mod_def0_i => sfp_present_i,
sfp_rate_select_o => sfp_rate_select_o,
sfp_mod_def1_b => sfp_scl_b,
sfp_mod_def2_b => sfp_sda_b,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_tx_fault_i => sfp_tx_fault_i,
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o => led_i2c,
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => sw_other,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i => line_ttl,
line_inv_i => line_invttl,
line_rear_i => line_rs485,
line_front_fs_i => ttlbar_nosig,
line_inv_fs_i => (others => '0'),
line_rear_fs_i => rs485_fs,
-- Thermometer line
thermometer_b => thermometer_b,
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o => led_syserr,
-- Bicolor LED signals
bicolor_led_state_i => bicolor_led_state,
bicolor_led_col_o => bicolor_led_col,
bicolor_led_line_o => bicolor_led_line,
bicolor_led_line_oen_o => bicolor_led_line_oen
);
--============================================================================
-- Channel output logic
--============================================================================
-- Front and rear panel outputs
ttl_o <= pulse_out when sw_ttl = '1' else
not pulse_out;
inv_o <= inv_n_i;
rs485_o <= pulse_out;
-- Channel terminations
sw_iterm_en <= sw_gp(1);
sw_oterm_en <= sw_gp(2);
iterm_en_o <= (others => sw_iterm_en);
oterm_en_o <= (others => sw_oterm_en);
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
gen_inv_ttl_leds : for i in 0 to 3 generate
inv_n(i) <= inv_n_i(i);
p_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inv_n_d0(i) <= '0';
inv_n_fedge_p(i) <= '0';
led_inv_cnt(i) <= (others => '0');
led_inv(i) <= '0';
else
inv_n_d0(i) <= inv_n(i);
inv_n_fedge_p(i) <= (not inv_n(i)) and inv_n_d0(i);
case led_inv(i) is
when '0' =>
if (inv_n_fedge_p(i) = '1') then
led_inv(i) <= '1';
end if;
when '1' =>
led_inv_cnt(i) <= led_inv_cnt(i) + 1;
if (led_inv_cnt(i) = (led_inv_cnt(i)'range => '1')) then
led_inv(i) <= '0';
end if;
when others =>
led_inv(i) <= '0';
end case;
end if;
end if;
end process p_pulse_led;
end generate gen_inv_ttl_leds;
-- LED outputs
led_front_o <= led_pulse;
led_inv_o <= led_inv;
led_rear_n_o <= not led_pulse;
--============================================================================
-- External logic for bicolor LED control
--============================================================================
-- Assign bicolor LED lines & columns to outputs
led_ttl_i2c_o <= bicolor_led_col(0);
led_oterm_wr_o <= bicolor_led_col(1);
led_iterm_syserror_o <= bicolor_led_col(2);
led_gf_syspw_o <= bicolor_led_col(3);
led_gp_2_4_o <= bicolor_led_col(4);
led_gp_1_3_o <= bicolor_led_col(5);
led_ctrl0_o <= bicolor_led_line(0);
led_ctrl1_o <= bicolor_led_line(1);
led_ctrl0_oen_o <= bicolor_led_line_oen(0);
led_ctrl1_oen_o <= bicolor_led_line_oen(1);
-- TTL mode (state of TTL switch)
bicolor_led_state( 1 downto 0) <= c_LED_GREEN when (sw_ttl = '1') else
c_LED_OFF;
-- Output termination enabled
bicolor_led_state( 3 downto 2) <= c_LED_GREEN when (sw_oterm_en = '1') else
c_LED_OFF;
-- Input termination enabled
bicolor_led_state( 5 downto 4) <= c_LED_GREEN when (sw_iterm_en = '1') else
c_LED_OFF;
-- Glitch filter enabled
bicolor_led_state( 7 downto 6) <= c_LED_GREEN when (sw_gp(0) = '1') else
c_LED_OFF;
-- General-purpose 4
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- General-purpose 3
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_OFF;
-- White Rabbit LED
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (led_syserr = '1') or
(c_gwvers(7 downto 4) = "0000" ) else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- General-purpose 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- General-purpose 1
bicolor_led_state(23 downto 22) <= c_LED_OFF;
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
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