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Commit f604eada authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Updated user guide 

- added pulse time-tagging
- moved glitch filter to outside the PG block in the pulse-rep figure
- updated the memory map and made it prettier
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
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doc/userguide/cern-title.tex
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......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill February 5, 2013
\hfill February 14, 2013
\vspace*{3cm}
......
doc/userguide/conv-regs.tex 0 → 100644
View file @ f604eada
\subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.45\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & Undefined (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TFMR & Tag FIFO Meta Register\\
0x30 & 0x00000000 & TFCYR & Tag FIFO Cycles Register \\
0x34 & 0x00000000 & TFTLR & Tag FIFO TAI Low Register \\
0x38 & 0x00000000 & TFTHR & Tag FIFO TAI High Register \\
0x3c & 0x00020000 & TFCSR & Tag FIFO Control and Status Register \\
\end{longtable}
}
\noindent Note 1: The SR is undefined on startup due to the fact that the
gateware version, switches and RTM fields may have different values.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x1e -- v1.14 \\ 0x20 -- v2.0
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board switches
\\
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ bit 1 -- SW1.2 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
0 -- line active \\ 1 -- line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: Communication watchdog timer status
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 - Reset bit unlocked \\ 0 - Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 - initiate logic reset \\ 0 - no reset
\end{small}
\item \begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVLR
} [\emph{read/write}]: TAI seconds counter bits 31..0
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVHR
} [\emph{read/write}]: TAI seconds counter bits 39..32
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFMR -- Tag FIFO Meta Register}
\label{app:conv-regs-tfmr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN
} [\emph{read-only}]: Channel mask
\\
Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFCYR -- Tag FIFO Cycles Register}
\label{app:conv-regs-tfcyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CYC[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CYC
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTLR -- Tag FIFO TAI Low Register }
\label{app:conv-regs-tftlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
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\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
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\hline
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\hline
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\hline
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\hline
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}
\begin{itemize}
\item \begin{small}
{\bf
TAI\_L
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTHR -- Tag FIFO TAI High Register}
\label{app:conv-regs-tfthr}
\vspace{11pt}
\noindent
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\begin{itemize}
\item \begin{small}
{\bf
TAI\_H
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFCSR -- Tag FIFO Control and Status Register }
\label{app:conv-regs-tfcsr}
\vspace{11pt}
\noindent
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\hline
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}
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: FIFO full flag
\\
1: FIFO is full\\0: FIFO is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: FIFO empty flag
\\
1: FIFO is empty\\0: FIFO is not empty
\end{small}
\item \begin{small}
{\bf
CLEAR\_BUS
} [\emph{write-only}]: FIFO clear
\\
write 1: clears FIFO \\write 0: no effect\\
Note that a clear will not delete the data in the FIFO, just bring the
read and write pointers at the same position.\\
\end{small}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: FIFO counter
\\
Number of data records currently being stored in FIFO.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
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doc/userguide/fig/timetag-arch.svg 0 → 100644
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doc/userguide/multiboot-regs.tex 0 → 100644
View file @ f604eada
\subsection{MultiBoot controller}
\label{app:multiboot-regs}
Base address: 0x040
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:multiboot-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:multiboot-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:multiboot-regs-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:multiboot-regs-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{FAR -- Flash Access Register}
\label{app:multiboot-regs-far}
\vspace{11pt}
\noindent
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\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
doc/userguide/userguide-conv-ttl-blo.tex
View file @ f604eada
......@@ -4,7 +4,7 @@
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames]{color}
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
......@@ -14,9 +14,14 @@
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
......@@ -48,6 +53,7 @@
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
......@@ -59,9 +65,7 @@
05-08-2013 & 1.04 & Memory map is now appendix \\
23-12-2013 & 1.05 & Added remote reprogramming support \\
10-01-2014 & 1.06 & Added SNMP access sub-section \\
28-01-2014 & 1.07 & Added Diagnostics section and moved remote resetting subsection to this section \\
31-01-2014 & 1.08 & Added manual pulse triggering sub-section \\
05-02-2014 & 1.09 & Added temperature and unique ID readout support \\
14-02-2014 & 2.00 & Added diagnostics section \\
\hline
\end{tabular}
}
......@@ -77,8 +81,10 @@
\listoffigures
\listoftables
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
FIFO & First-In-First-Out (memory) \\
FPGA & Field-Programmable Gate Array \\
I$^2$C & Inter-Integrated Circuit \\
MIB & Management Information Base \\
......@@ -87,7 +93,9 @@
RTM & Rear Transition Module \\
SFP & Small Form-factor Pluggable (connector) \\
SNMP & Simple Network Management Protocol \\
TAI & International Atomic Time (French abbreviation) \\
VME & VERSAmodule Eurocard \\
WR & White Rabbit \\
\end{tabular}
%======================================================================================
......@@ -126,6 +134,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\item unique board ID and temperature readout
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item input pulse time-tagging
\item manual pulse triggering
\end{itemize}
\item Remote reprogramming over I$^2$C lines on VME P1 connector
......@@ -211,6 +220,7 @@ LEDs are \textit{off}.
\label{tbl:status-leds}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.75\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{LED}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -233,12 +243,12 @@ LEDs are \textit{off}.
%--------------------------------------------------------------------------------------
\subsubsection{SFP connector}
This connector is used to add White Rabbit support to the CONV-TTL-BLO boards.
If an optic fibre cable is connected to this socket, White Rabbit precise
This connector is used to add White Rabbit (WR) support to the CONV-TTL-BLO boards.
If an optic fibre cable is connected to this socket, WR precise
time-stamping can be added to CONV-TTL-BLO. Four status LEDs above the connector are provide
to show the status of the White Rabbit link.
to show the status of the WR link.
White Rabbit is currently not supported by the FPGA gateware.
WR is currently not supported by the FPGA gateware.
%--------------------------------------------------------------------------------------
\subsubsection{TTL inputs and outputs}
......@@ -326,6 +336,7 @@ the used switches are also listed in Table~\ref{tbl:switches}.
\label{tbl:switches}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.85\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Switch}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -384,6 +395,7 @@ pulses.
\label{tbl:pulse-def-ttl}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
......@@ -393,7 +405,7 @@ pulses.
$V_{IL}$ & Input pulse low-level amplitude (2) & 0.7 & & 1.6 & V \\
$V_{OH}$ & Output pulse high-level amplitude & 2.4 & 3.3 & 5 & V \\
$V_{OL}$ & Output pulse low-level amplitude & & 0 & 0.7 & V \\
$t_{p,i}$& Input pulse width & 50 & & & ns \\
$t_{p,i}$& Input pulse width & 100 & & & ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 1 & 3.2 & 4.9 & ns \\
......@@ -414,6 +426,7 @@ by the FPGA gateware. \\
\label{tbl:pulse-def-blo}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
......@@ -423,7 +436,7 @@ by the FPGA gateware. \\
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 23 & 24 & 25 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 50 & & 3900& ns \\
$t_{p,i}$& Input pulse width & 100 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
......@@ -485,17 +498,18 @@ pass through a part of the circuit. The grey DC signals are the signals when no
plugged into a channel.
\begin{figure}[htbp]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-rep}}
\centerline{\includegraphics[width=.95\textwidth]{fig/pulse-rep}}
\caption{Pulse repetition mechanism}
\label{fig:pulse-rep}
\end{figure}
The pulse generator (PG) block in the FPGA generates $t_{p,o}$ wide (Table~\ref{tbl:pulse-def-ttl})
TTL pulses at its output on the rising edge of its input. It therefore expects TTL pulses at
its input. The rest of the logic external to this block is used to accommodate for TTL-BAR
and blocking pulses.
its input. For more information about the implementation of the PG block, refer to the
CONV-TTL-BLO HDL Guide~\cite{ctb-hdlguide}.
First, the OR gates at the PG input indicate the condition for a pulse to
The rest of the logic external to the PG block is used to accommodate for TTL-BAR
and blocking pulses. First, the OR gates at the PG input indicate the condition for a pulse to
be regenerated. The conditions for pulse generation are either that pulse is manually triggered
as described in Section~\ref{sec:diag-man-trig}, or that a pulse arrives on either of the inputs of a channel
(TTL or TTL-BAR on the front panel, or blocking on the rear panel).
......@@ -522,16 +536,26 @@ checks if the line is high for more than 100~$\mu$s when the TTL selection switc
set for TTL-BAR signals and disables the TTL input line to the PG, thus allowing for
blocking pulses arriving on the rear panel to be detected by the PG.
After the two types of signals are ORed together to form a trigger to the PG block,
they can optionally be passed through a glitch filter (the GF block in Figure~\ref{fig:pulse-rep}).
More details about this glitch filter can be found in Section~\ref{sec:pulse-jit}.
One pulse counter is implemented for each channel. This pulse counter increments when a
rising edge is detected on the output of the OR gate between the two inputs types. More
details about the pulse counters can be found in Section~\ref{sec:diag-pulse-cnt}.
A rising edge on a pulse also triggers storing the value of a user-settable time tag to
a first-in-first-out (FIFO) memory. More details about the time-tagging of pulses
can be found in Section~\ref{sec:diag-pulse-timetag}.
The PG block can also be triggered by a "manual" pulse. More details about this feature
can be found in Section~\ref{sec:diag-man-trig}.
\textbf{\textit{Note that due to the nature of TTL-BAR signals (high when idle), when the cable is removed
from the connector, or when the pulse sending device upstream of the CONV-TTL-BLO is turned off,
the channel line goes high due to the Schmitt trigger at the input of the CONV-TTL-BLO, and
a pulse will be generated on the output.}}
One pulse counter is implemented for each channel. As can be seen in Figure~\ref{fig:pulse-rep},
this pulse counter increments when a rising edge is detected on the output of the OR gate
between the two inputs types. More details about the pulse counters can be found in
Section~\ref{sec:diag-pulse-cnt}.
%--------------------------------------------------------------------------------------
% SUBSEC: Pulse jitter and delay
%--------------------------------------------------------------------------------------
......@@ -559,6 +583,26 @@ glitch filter which rejects any pulses narrower than 50~ns, but introduces a 50~
on the leading edge of the output signal. Jitter appears in the form of an uncertainty on when
a pulse is output.
Since an input pulse is asynchronous to the sampling clock, it may arrive
before or after the sampling clock's rising edge. If it arrives before the sampling clock rising
edge, it is sampled on the current cycle. However, if the input pulse arrives after the rising edge,
it will get sampled on the next clock rising edge. The output pulse may therefore present
an uncertainty on when its leading edge arrives; this uncertainty (shown in Figure~\ref{fig:tpd-jit}),
which is the output jitter, is based on the 50~ns sampling clock.
When SW1.1 is in the \textbf{OFF} (default) position, the glitch filter is disabled and the
pulse signal is regenerated at the output without being sampled with an on-board clock. This
yields jitter-free pulses at the output, but a glitch on the input will lead to a pulse being
generated at the output.
The glitch filter internal to the PG block may be enabled when the environment where the
board operates is noisy. A noisy environment may lead to glitches induced on the
signal lines and thus unwanted pulses on the output of the CONV-TTL-BLO. When the
environment is not so noisy, or when the 50~ns jitter is deemed to be an issue, SW1.1
can be left in the \textbf{OFF} position.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth,keepaspectratio]{fig/tpd-jit}}
\caption{Output pulse delay and jitter}
......@@ -570,6 +614,7 @@ a pulse is output.
\label{tbl:pulse-tpd-jit}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
......@@ -594,26 +639,6 @@ a pulse is output.
\noindent Note 1: If the glitch filter is enabled, it adds an extra 350~ns delay to $t_{PD}$.
\vspace*{11pt}
Since an input pulse is asynchronous to the sampling clock, it may arrive
before or after the sampling clock's rising edge. If it arrives before the sampling clock rising
edge, it is sampled on the current cycle. However, if the input pulse arrives after the rising edge,
it will get sampled on the next clock rising edge. The output pulse may therefore present
an uncertainty on when its leading edge arrives; this uncertainty (shown in Figure~\ref{fig:tpd-jit}),
which is the output jitter, is based on the 50~ns sampling clock.
When SW1.1 is in the \textbf{OFF} (default) position, the glitch filter is disabled and the
pulse signal is regenerated at the output without being sampled with an on-board clock. This
yields jitter-free pulses at the output, but a glitch on the input will lead to a pulse being
generated at the output.
The glitch filter internal to the PG block may be enabled when the environment where the
board operates is noisy. A noisy environment may lead to glitches induced on the
signal lines and thus unwanted pulses on the output of the CONV-TTL-BLO. When the
environment is not so noisy, or when the 50~ns jitter is deemed to be an issue, SW1.1
can be left in the \textbf{OFF} position.
%======================================================================================
% SEC: Communicating to the CONV-TTL-BLO
%======================================================================================
......@@ -661,6 +686,7 @@ data to the board. As names suggest, \textit{readreg} reads a board register, w
\label{tbl:cmds}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Command}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -678,7 +704,8 @@ data to the board. As names suggest, \textit{readreg} reads a board register, w
\end{table}
An example of retrieving the CONV-TTL-BLO ID of a CONV-TTL-BLO plugged into VME slot 2 of the crate
\textit{some-crate} is given below. Since the ID can be retrieved from address 0x0 (see Appendix~\ref{app:memmap-conv-regs}),
\textit{some-crate} is given below. The converter board ID can be retrieved from the board ID
register at address 0x000 (BIDR -- see Appendix~\ref{app:conv-regs-bidr}),
if the board is present in slot 2, the command should yield the ASCII string \textbf{TBLO}.
\begin{verbatim}
......@@ -731,7 +758,6 @@ password:**********
%------------------------------------------------------------------------------
% SUBSEC: SNMP
%------------------------------------------------------------------------------
\pagebreak
\subsection{SNMP}
\label{sec:comm-snmp}
......@@ -828,7 +854,7 @@ The following diagnostics features are implemented on the CONV-TTL-BLO:
\label{sec:diag-bid}
All converter boards have a board identification register (BIDR -- see
Appendix~\ref{app:memmap-bidr}) at address \textbf{0x000}. This register is
Appendix~\ref{app:conv-regs-bidr}) at address \textbf{0x000}. This register is
a read-only 32-bit register containing the hex values for the ASCII code
describing the functionality of the converter board.
......@@ -842,7 +868,7 @@ for TTL-to-blocking converter.
\label{sec:diag-gwvers}
The gateware version can be read from the least significant eight bits of the
status register (SR -- see Appendix~\ref{app:memmap-sr}). The gateware version
status register (SR -- see Appendix~\ref{app:conv-regs-sr}). The gateware version
is split into major and minor version numbers. Both numbers are decimal numbers.
The major version number increments on major changes in the gateware, such as
the implementation of new blocks. The minor version increments on bug fixes.
......@@ -876,10 +902,11 @@ details about this data and how to obtain it can be found in the device's
datasheet~\cite{ds18b20}.
\begin{table}[h]
\caption{Data from thermometer (see~\cite{ds18b20})}
\caption{Data from thermometer}
\label{tbl:thermo-data}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Data}} & \multicolumn{1}{c}{\textbf{Length}} &
......@@ -902,6 +929,7 @@ can be found in Table~\ref{tbl:thermo-scripts}.
\caption{Scripts needed for remote reprogramming}
\label{tbl:thermo-scripts}
\centerline {
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Script}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -925,7 +953,7 @@ can be found in Table~\ref{tbl:thermo-scripts}.
\label{sec:diag-sw-rtmdet}
The state of the on-board switches and that of the RTM detection lines can
also be read from the SR (see Appendix~\ref{app:memmap-sr}).
also be read from the SR (see Appendix~\ref{app:conv-regs-sr}).
In the case of the switches, the raw state of the FPGA inputs is reflected on
the SR bits. Since an ON switch pulls the line to GND, a '0' value on one
......@@ -961,9 +989,98 @@ is shown in Figure~\ref{fig:pulse-cnt}.
On a rising edge of a pulse from either a TTL or a blocking input, the pulse
counter is incremented and stored to the channel's pulse counter register
(CHxPCR -- see Appendix~\ref{app:memmap-chpcr}). The CHxPCR is a read-write register
(CHxPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR is a read-write register
that can be written at any time via I$^2$C with a user-defined value.
%------------------------------------------------------------------------------
% SUBSEC: Pulse counters
%------------------------------------------------------------------------------
\subsection{Pulse time-tagging}
\label{sec:diag-pulse-timetag}
The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timetag-arch}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-arch}}
\caption{Time-tag architecture}
\label{fig:timetag-arch}
\end{figure}
Every time a pulse arrives on a channel, a time-tag sample is stored to a 128-deep
FIFO memory and the head of the FIFO advances. The head of the FIFO always points to the
last received pulse, as long as the FIFO is not full. When the FIFO is full, no more
time-tag samples are stored until the FIFO is read.
Two time-tags are available on the CONV-TTL-BLO. These time-tags are listed in
Table~\ref{tbl:timetags}. When White-Rabbit (WR) is present, the precise centralized
and synchronized timing from the WR network is used. When WR is not present, the local
time tag is used. Note that due to the fact that this time-tag is unsynchronized,
it will differ slightly between two different boards in a crate.
Each time-tag sample consists of a cycles value, which counts 8~ns cycles, and a TAI seconds
value.
\begin{table}[h]
\caption{Time tag types}
\label{tbl:timetags}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Type}} & \multicolumn{1}{c}{\textbf{Resolution}}
& \multicolumn{1}{c}{\textbf{Description}} \\
\hline
WR & 8~ns & \textbf{\textit{Currently not implemented}} \newline
Precise, centralized and synchronized time-tag \newline
Obtained and configurable via WR \newline
Resolution: \textbf{8~ns} \\
Local & 8~ns & Local, unsynchronized time-tag \newline
Obtained by counting the ticks of a 125~MHz clock signal \newline
Can be set remotely by writing the TAI value registers (TVL/HR) \newline
Resolution: \textbf{8~ns} \\
\hline
\end{tabular}
}
\end{table}
The FIFO memory is not entirely accessible in the addressing space,
instead the head of the FIFO is always accessible via the meta, cycle and TAI tag
FIFO registers in the converter board registers (TFMR, TFCYR, TFTL/HR -- see
Appendix~\ref{app:conv-regs}).
The tag FIFO cycle and TAI registers (TFCYR, TFTL/HR) contain the actual time tag
values. The tag FIFO meta register (TFMR) completes these registers with information
about the current FIFO time-tag sample, such as the channel number that triggered
the storing of the current time tag and whether this time-tag was obtained via WR
or not.
The control and status register (TFCSR -- see Appendix~\ref{app:conv-regs-tfcsr}) can
be used to check the status of the FIFO and clearing it. Note that clearing the FIFO
will not erase the memory, but simply bring the read and write pointers of the FIFO
to the same position.
Also note that in order to properly read a time tag value in the FIFO and advance
the read pointer, a read from the TFMR is needed. If the user only reads one of the
other registers without reading the TFMR, the read pointer of the FIFO will not
advance. A full read cycle of a FIFO sample should look like this:
\begin{itemize}
\item read TFMR to obtain meta data about the tag FIFO sample and advance
the FIFO read pointer
\item read TFCYR to obtain the number of 8~ns cycles when the sample was stored
\item read TFTLR to obtain the lower part of the TAI counter
\item read TFTHR to obtain the upper part of the TAI counter
\end{itemize}
The E (empty) or F (full) bits of the TFCSR can be used to know when to stop reading
the FIFO. Of the two, it is recommended to use the E bit and read the FIFO while
this bit is cleared ('0').
When the FIFO is full of samples, the FPGA will not store any more samples
and the F bit will be set. Note that the USED field will indicate 0 samples stored
at this time.
%------------------------------------------------------------------------------
% SUBSEC: Remote reset
%------------------------------------------------------------------------------
......@@ -971,7 +1088,7 @@ that can be written at any time via I$^2$C with a user-defined value.
\label{sec:diag-remote-reset}
The user can remotely reset the FPGA logic inside the CONV-TTL-BLO by writing to
the board's control register at address \textbf{0x008} (see Appendix~\ref{app:memmap-cr})
the board's control register at address \textbf{0x008} (see Appendix~\ref{app:conv-regs-cr})
to first unlock the RST bit and then write it high to initiate the reset. When the
reset is initiated, a 100~ms reset pulse is applied to the logic.
......@@ -1018,7 +1135,7 @@ triggering is "password" protected.
In order to manually trigger a pulse, a user should write a four-byte "magic sequence"
(the "password") to the MPT (manual pulse trigger) field in the board's control
register at address 0x004 (CR -- see Appendix~\ref{app:memmap-cr}). The MPT
register at address 0x004 (CR -- see Appendix~\ref{app:conv-regs-cr}). The MPT
field is dual-purpose, as shown in Figure~\ref{fig:cr-mpt}. As shown in
Table~\ref{tbl:man-trig-magic}, prior to sending a pulse, the MPT field should be written
with the magic sequence, followed by a channel number in the range \textbf{1..6}.
......@@ -1034,6 +1151,7 @@ with the magic sequence, followed by a channel number in the range \textbf{1..6}
\label{tbl:man-trig-magic}
\centerline
{
%\rowcolors{2}{white}{gray!25}
\begin{tabular}{c c c c c}
\hline
\textbf{Byte 0} & \textbf{Byte 1} & \textbf{Byte 2} & \textbf{Byte 3} & \textbf{Byte 4}\\
......@@ -1057,7 +1175,7 @@ sequence is not as expected, the logic returns to waiting for the first byte
of the magic sequence.
\begin{figure}[h]
\centerline{\includegraphics[width=.49\textwidth]{fig/man-trig-fsm}}
\centerline{\includegraphics[width=.6\textwidth]{fig/man-trig-fsm}}
\caption{Manual pulse triggering logic}
\label{fig:man-trig-fsm}
\end{figure}
......@@ -1133,6 +1251,7 @@ The workflow for remote reprogramming is shown in Table~\ref{tbl:reprog-workflow
\caption{MultiBoot workflow}
\label{tbl:reprog-workflow}
\centerline {
\rowcolors{2}{white}{gray!25}
\begin{tabular}{c p{.7\textwidth}}
\hline
\textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\
......@@ -1189,6 +1308,7 @@ Table~\ref{tbl:reprog-flash-memmap}.
\caption{Flash memory map}
\label{tbl:reprog-flash-memmap}
\centerline{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l l}
\hline
\multicolumn{3}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -1227,6 +1347,7 @@ needed to run the script.
\caption{Scripts needed for remote reprogramming}
\label{tbl:reprog-scripts}
\centerline {
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Script}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -1319,7 +1440,7 @@ programmed into the flash.
% APP: Getting started
%======================================================================================
\section{Getting started with the CONV-TTL-BLO}
\label{sec:app-get-started}
\label{app:get-started}
\begin{enumerate}
\item Plug in the CONV-TTL-RTM board into the rear part of the VME crate.
......@@ -1359,7 +1480,7 @@ programmed into the flash.
% APP: Typical use cases
%======================================================================================
\section{Typical use cases}
\label{sec:app-use-cases}
\label{app:use-cases}
%--------------------------------------------------------------------------------------
% SUBSEC: 1 to 12 blocking pulses
......@@ -1425,360 +1546,28 @@ $reg. index = \frac{addr}{4} + 1$
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Periph.}} & \multicolumn{2}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{Description}} \\
& \multicolumn{1}{c}{\textbf{Base}} & \multicolumn{1}{c}{\textbf{End}} & \\
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
Board regs & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
Thermo & 0x080 & 0x084 & Thermometer chip \\
Board registers & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
Thermometer & 0x080 & 0x084 & Thermometer chip \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
% SUBSEC: conv_regs
%------------------------------------------------------------------------------
\subsection{Converter board registers}
\label{app:memmap-conv-regs}
\indent Base address: 0x000
\begin{table}[h]
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & BIDR & Board ID register \\
0x04 & SR & Status register \\
0x08 & CR & Control register \\
0x0c & CH1PCR & Channel 1 Pulse Counter Register \\
0x10 & CH2PCR & Channel 2 Pulse Counter Register \\
0x14 & CH3PCR & Channel 3 Pulse Counter Register \\
0x18 & CH4PCR & Channel 4 Pulse Counter Register \\
0x1c & CH5PCR & Channel 5 Pulse Counter Register \\
0x20 & CH6PCR & Channel 6 Pulse Counter Register \\
\end{tabular}
\end{table}
%------------------------------------------------------------------------------
\subsubsection{Board ID Register}
\label{app:memmap-bidr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..0 & ID & R/O & 0x54424c4f & Board ID \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l l}
\textbf{Field} & \textbf{Description} \\
ID & Board ID (ASCII string \textbf{TBLO}) \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{Status Register}
\label{app:memmap-sr}
\begin{tabular}{l l c c p{.35\textwidth}}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
7..0 & GWVERS & R/O & X & Gateware version \\
15..8 & SWITCHES & R/O & X & Switch status \\
21..16 & RTM & R/O & X & RTM detection lines \\
22 & CWDTO & R/W & 0 & Communication watchdog timeout \\
31..23 & \textit{Reserved} & -- & X & \\
\end{tabular}
\noindent
{
\begin{tabular}{l p{.8\textwidth}}
\textbf{Field} & \textbf{Description} \\
GWVERS & Gateware version \newline
-- leftmost nibble \textit{hex value} is major release \textit{decimal value} \newline
-- rightmost nibble \textit{hex value} is minor release \textit{decimal value} \newline
e.g. \newline
0x11 -- v1.1\newline
0x1e -- v1.14 \newline
0x20 -- v2.0 \newline
etc. \\
SWITCHES & Current switch status \newline
bit 0 -- SW1.1 \newline
bit 1 -- SW1.2 \newline
... \newline
bit 7 -- SW2.4 \newline
\textbf{1} -- switch is \textbf{OFF} \newline
\textbf{0} -- switch is \textbf{ON} \\
RTM & RTM detection lines status~\cite{rtm-det} \newline
\textbf{0} -- line active \newline
\textbf{1} -- line inactive \\
CWDTO & Communication watchdog timeout status \newline
\textbf{0} -- watchdog idle \newline
\textbf{1} -- communication error has occured and watchdog timer fired \newline
This bit is cleared by writing a '1' to it \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{Control Register}
\label{app:memmap-cr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
0 & RST\_UNLOCK & R/W & 0 & Reset bit unlock \\
1 & RST & R/W & 0 & Reset bit \\
9..2 & MPT & W/O & 0 & Manual Pulse Trigger \\
31..10 & \textit{Reserved} & -- & X & \\
\end{tabular}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
RST\_UNLOCK & Reset bit unlock \newline
\textbf{0} -- RST bit locked, cannot be written \newline
\textbf{1} -- RST bit unlocked, can be written \\
RST & Reset bit \newline
\textbf{0} -- Idle \newline
\textbf{1} -- Initiate a system reset \newline
This bit needs to be unlocked by writing a '1' to the RST\_UNLOCK bit in a
previous cycle. A write to this bit while RST\_UNLOCK = '0' has no effect. \newline
Writing this bit to 1 with RST\_UNLOCK = '1' will issue a system reset and
the communication to the board will be lost for approx. 100~ms \\
MPT & Control bits for manual pulse trigger sequence \newline
To trigger a pulse, write this sequence to the field: \newline
\textbf{0xde} -- Passbyte 1 \newline
\textbf{0xad} -- Passbyte 2 \newline
\textbf{0xbe} -- Passbyte 3 \newline
\textbf{0xef} -- Passbyte 4 \newline
Channel number in range 1..6 \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{Channel Pulse Counter Registers}
\label{app:memmap-chpcr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..0 & CHxPC & R/W & 0 & Pulse counter register value\\
\end{tabular}
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection{MultiBoot module}
\label{app:memmap-multiboot}
\indent Base address: 0x040
\vspace*{11pt}
\centerline
{
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & CR & Control Register \\
0x04 & SR & Status Register \\
0x08 & GBBAR & Golden Bitstream Base Address Register \\
0x0c & MBBAR & Multiboot Bitstream Base Address Register \\
0x10 & FAR & Flash Access Register \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{CR -- Control Register}
\label{app:memmap-multiboot-cr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..18 & \textit{Reserved} & -- & X & \\
17 & IPROG & R/W & 0 & IPROG bit \\
16 & IPROG\_UNLOCK & R/W & 0 & IPROG unlock bit \\
15..7 & \textit{Reserved} & -- & X & \\
6 & RDCFGREG & R/W & 0 & Read config register \\
5..0 & CFGREGADR & R/W & 0 & Config register address \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
\textit{Reserved} & Write as '0'; read undefined. \\
IPROG & Start IPROG sequence \newline
\textbf{0} -- Idle \newline
\textbf{1} -- Start the IPROG sequence \newline
This bit needs to be unlocked by setting the IPROG\_UNLOCK bit in a previous cycle. Any
write to this bit with IPROG\_UNLOCK = '0' has no effect. \newline
Writing this bit to '1' with IPROG\_UNLOCK = '1' will issue the IPROG sequence and
communication to the board will be lost until reprogramming is completed \\
IPROG\_UNLOCK & Unlock bit for the IPROG command \newline
\textbf{0} -- IPROG bit locked, cannot be written \newline
\textbf{1} -- IPROG bit unlocked, can be written \\
RDCFGREG & Read FPGA configuration register \newline
\textbf{0} -- Idle \newline
\textbf{1} -- Initiate read from configuration register at address CFGREGADR \newline
This bit is automatically cleared by hardware. \\
CFGREGADR & The address of the FPGA configuration register to read (see Configuration Registers
section in~\cite{ug380}) \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{SR -- Status Register}
\label{app:memmap-multiboot-sr}
\begin{tabular}{l l c c p{.3\textwidth}}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..18 & \textit{Reserved} & -- & X & \\
17 & MWDTO & R/W & 0 & Multiboot watchdog timeout \\
16 & IMGVALID & R/O & 0 & Image register is valid \\
15..0 & CFGREGIMG & R/O & 0 & Config. register image \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
\textit{Reserved} & Write as '0'; read undefined. \\
MWDTO & The watchdog of the MultiBoot FSM has timed out \newline
This bit is cleared by writing a '1' to it \\
IMGVALID & A read has been performed from the FPGA configuration
register at address CR.CFGREGADR, and its value is
present in CFGREGIMG \\
CFGREGIMG & Contains the value of the FPGA configuration register
(see Configuration Registers section in~\cite{ug380});
validated by the IMGVALID bit \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:memmap-multiboot-gbbar}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..24 & OPCODE & R/W & 0 & Flash chip read op-code \\
23..0 & GBA & R/W & 0 & Golden Bitstream Address \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
OPCODE & Op-code for the flash chip read (or fast-read) command. Get
this value from the flash chip datasheet \\
GBA & Start address of the Golden bitstream on the flash chip \\
\end{tabular}
}
\vspace*{11pt}
%Guidelines on selecting a GBBAR:
%
%\begin{itemize}
% \item When generating the Header image via Xilinx ISE, the GBA is (normally)
% automatically set by the software to 0x44
% \item If different than the default, the starting address of the Golden
% bitstream should be set to a flash sector boundary
%\end{itemize}
%------------------------------------------------------------------------------
\subsubsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:memmap-multiboot-mbbar}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..24 & OPCODE & R/W & 0 & Flash chip read op-code \\
23..0 & MBA & R/W & 0 & MultiBoot Bitstream Address \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
OPCODE & Op-code for the flash chip read (or fast-read) command. Get
this value from the flash chip datasheet \\
MBA & Start address of the MultiBoot bitstream on the flash chip \\
\end{tabular}
}
\vspace*{11pt}
%Guidelines on selecting an MBBAR:
%
%\begin{itemize}
% \item The MultiBoot bitstream should start on a flash sector boundary.
%\end{itemize}
%------------------------------------------------------------------------------
\subsubsection{FAR -- Flash Access Register}
\label{app:memmap-multiboot-far}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..29 & \textit{Reserved} & -- & 0 & Flash chip read op-code \\
28 & READY & R & 1 & SPI access status \\
27 & CS & R/W & 0 & SPI chip select \\
26 & XFER & R/W & 0 & Start SPI transfer \\
25..24 & NBYTES & R/W & 0 & Number of bytes to send \\
23..16 & DATA[2] & R/W & 0 & Data at offset 2 \\
15..8 & DATA[1] & R/W & 0 & Data at offset 1 \\
7..0 & DATA[0] & R/W & 0 & Data at offset 0 \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
\textit{Reserved} & Write as '0'; read undefined \\
READY & SPI transfer ready; NBYTES have been sent to the flash chip,
and NBYTES read from the chip present in DATA fields \\
CS & SPI chip select. Note that this pin has opposite polarity
than the normal SPI chip select pin: \newline
\textbf{0} -- Flash chip is not selected (CS pin = 1) \newline
\textbf{1} -- Flash chip is selected (CS pin = 0) \\
XFER & Start SPI transfer \newline
\textbf{1} -- Idle \newline
\textbf{1} -- Start SPI transfer \newline
This bit is automatically cleared by hardware \\
NBYTES & Number of DATA fields to send in one transfer \newline
\textbf{0} -- Send 1 byte (DATA[0]) \newline
\textbf{1} -- Send 2 bytes (DATA[0], DATA[1]) \newline
\textbf{2} -- Send 3 bytes (DATA[0], DATA[1], DATA[2]) \newline
\textbf{3} -- \textit{Reserved} \\
DATA[2] & Write this register with the value of data byte 2 \newline
After an SPI transfer, this register contains the value of
data byte 2 read from the flash \\
DATA[1] & Write this register with the value of data byte 1 \newline
After an SPI transfer, this register contains the value of
data byte 1 read from the flash \\
DATA[0] & Write this register with the value of data byte 0 \newline
After an SPI transfer, this register contains the value of
data byte 0 read from the flash \\
\end{tabular}
}
\include{multiboot-regs}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
......@@ -1792,11 +1581,15 @@ $reg. index = \frac{addr}{4} + 1$
\centerline
{
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & OWCSR & One-Wire Control and Status Register \\
0x04 & OWCDR & One-Wire Clock Divider Registers \\
\end{tabular}
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
......@@ -1804,6 +1597,10 @@ $reg. index = \frac{addr}{4} + 1$
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%------------------------------------------------------------------------------
\end{appendices}
......
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