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Conv TTL Blocking
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\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\begin{document}
\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\begin{abstract}
This document describes the CONV-TTL-BLO board, a blocking pulse repeater
board in double height VME format, intended to replace the following boards:
\begin{itemize}
\item 8 channel repeater
\item 16 channel repeater
\item CTDAC
\item LA-BLO-TTL
\item LAF-BLO-TTL
\item LASB-TTL-BLO
\item LA-GATE
\item LA-TTL-BLO
\item LAPF-TTL-BLO \footnote{These boards have a 4~$\mu$s pulse width.}
\end{itemize}
\end{abstract}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
\section*{List of abbreviations}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{RTM} & Rear Transition Module \\
\textit{RTMM} & RTM Motherboard \\
\textit{RTMP} & RTM Piggyback \\
\textit{SFP} & Small form-factor pluggable (in the context of SFP connectors) \\
\end{tabular}
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
CONV-TTL-BLO is a board intended for replicating blocking and TTL pulses, providing six
totally independent replication channels. The shape of the pulses is defined in
Sec.~\ref{sec:pulse-def}. CONV-TTL-BLO works together with two more boards:
CONV-TTL-RTM and CONV-TTL-RTM-BLO (see Table~\ref{tbl:boards}.
CONV-TTL-BLO contains all the active circuitry and is connected as a front module
to a VME64x backplane. CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear
part of the crate and provide, in the rear panel, the connectivity of the I/O blocking
lines. Every channel offers, in the rear panel, three blocking pulse outputs and one
blocking pulse input.
CONV-TTL-RTM is a motherboard attached to the rear transition module (RTM) of the P2
VME64x connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides over-voltage protection for all the I/Os of all the channels.
CONV-TTL-RTM-BLO is an RTM piggyback (RTMP) board mounted on CONV-TTL-RTM. It contains all the
LEMO 00 connectors and pulse LEDs provided on the rear panel.
\begin{table}[htdp]
\caption{Boards for Blocking repetition}
\label{tbl:boards}
\centerline
{
%\begin{turn}{90}
\begin{tabular}{l l l}
\hline
\multicolumn{1}{c}{\textbf{Board}} & \multicolumn{1}{c}{\textbf{Connection}} & \multicolumn{1}{c}{\textbf{Front panel ports}} \\
\hline
\textit{CONV-TTL-BLO} & Front & SFP \\
& & TTL Blocking triggers \\
& & TTL Blocking output replica \\
& & inverters \\
\textit{CONV-TTL-RTM} & Back & - \\
\textit{CONV-TTL-RTM-BLO} & Back & Blocking Pulse input \\
&& Blocking Pulse outputs\\
\hline
\end{tabular}
}
%\end{turn}
\end{table}
%======================================================================================
% SEC: Panels
%======================================================================================
%\pagebreak
\section{Getting Started}
\label{sec:getting-started}
This section provides a description on testing CONV-TTL-BLO boards for basic functionality. The following steps should
be followed in order to test the board.
%The steps listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
%CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
%such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
\begin{enumerate}
\item Plug in a front module card to the ELMA crate. Turn on power to the crate and program
the Spartan-6 FPGA.
\item Check that the \textit{PW} LED lights \textit{green} and the \textit{ERR} LED lights \textit{red}. %and \textit{I2C} LEDs light \textit{red}.
The \textit{TTL\_N} LED may also be lit. If it is and the LED is \textit{green}, then the LEVEL
switch is set for INV-TTL pulses.
\item Make sure the LEVEL switch is set for TTL pulses (see Sec.~\ref{sec:ttl-inp}).
% \item Connect to an ELMA crate via TELNET, using the following command on the command line:
%
% \begin{verbatim}
%$ telnet 137.138.192.90
%Trying 137.138.192.90...
%Connected to 137.138.192.90.
%Escape character is '^]'.
%login:user
%password USER
%%>
% \end{verbatim}
%
% \item If the TELNET access is successful, the user should now be presented with a command line
% to the SysMon board. To test basic SysMon functionality, run a \verb=voltage= command on the
% SysMon, which should output the following:
%
% \begin{verbatim}
%%>voltage
%
%
%----------------------------Sensor List---------------------------
%
%--no--Name-------------Type----Value--Unit---State------------------
%
%* 2 +3.3V Thr 3.31 V Ok
%* 3 +5V Thr 5.01 V Ok
%* 4 +12V Thr 12.09 V Ok
%* 5 -12V Thr -12.38 V Ok
% \end{verbatim}
%
% \item It can now be proceeded to reading a register from the CONV-TTL-BLO boards. The \verb=readreg=
% command can be used for this purpose. Assuming a CONV-TTL-BLO board in VME slot 1, reading register
% I2C\_CTR0 at address 0x40 (see Sec. \ref{sec:internal-regs}) is done as follows:
%
% \begin{verbatim}
%%>readreg 1 17
% Read Data: 004042BC
% \end{verbatim}
%
% \item The output of the command should be as above, yielding the default value of the I2C\_CTR0 register.
% The \textit{I2C} LED on the front panel should also be lit \textit{green} now. It can now be proceeded to checking
% the pulse repetition mechanisms.
\item \label{item:pulse-first} First, connect one end of a cable with LEMO 00 connectors at both ends to the TTL input port of channel 1
on the front panel.
\item Configure a pulse generator to output TTL level pulses (\textit{max. 5V}) at a frequency of about 1~Hz
with a pulse length of approx. 1~$\mu$s and connect the other end of the cable to the pulse generator.
The LED of the corresponding channel should light for 96~ms when a pulse arrives. A TTL pulse should be
replicated at the TTL output of channel 1. Check (using e.g., an oscilloscope) that the TTL pulse has a width of
1~$\mu$s and a 3.3~V amplitude.
\item Connect a CONV-TTL-RTM board (with attached CONV-TTL-BLO-RTM) to the back-plane of the ELMA,
on the same VME slot as the front module. The \textit{ERR} LED should turn off. The rear panel pulse status LED
on channel 1 should be lit for 96~ms to signal pulses are being output on the channel. Check that the pulse width
on the output connectors of the rear panel is approx. 1~$\mu$s and the amplitude 24~V.
\item Disconnect the LEMO cable from the front panel and configure the pulse generator for 15~V pulse amplitude, keeping
the pulse width to approx. 1~$\mu$s.
\item Connect the LEMO cable to the input port of channel 1 on the rear panel. The channel 1 LEDs on both front and rear panels
should be lit for 96~ms. Measure that the output pulse on channel 1 is a blocking level pulse with approx. 1~${\mu}$s pulse
width and 24~V in amplitude.
\item \label{item:pulse-last}Finally, measure on the front panel of the front module that on channel 1 the output pulse is 1~${\mu}$s long and 3.3~V.
\item Repeat steps~\ref{item:pulse-first}-\ref{item:pulse-last} for all remaining five channels.
\end{enumerate}
%======================================================================================
% SEC: Panels
%======================================================================================
\section{Front and Rear Panels}
\label{sec:front-panel}
Two panels exist in the context of the pulse repeater boards. The first of these is the
\textit{front panel}, which corresponds to CONV-TTL-BLO boards and offers various status
LEDs, as well as various connectors for TTL and INV-TTL (see Sec.~\ref{sec:pulse-def}) pulses and White Rabbit.
The second is the \textit{rear panel}, located on the other side of the backplane and
corresponding to CONV-TTL-RTM-BLO boards. The rear panel offers blocking pulse connectors
and status LEDs for pulse arrival confirmation.
\subsection{Front panel}
The front panel of CONV-TTL-BLO boards is shown in Fig.~\ref{fp}. It consists
of status LEDs and several ports, divided in four sections from top to bottom:
\begin{itemize}
\item System status LEDs;
\item Small form-factor pluggable (SFP) connector;
\item TTL pulse connectors;
\item INV-TTL pulse connectors.
\end{itemize}
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=.5, keepaspectratio]{fig/front-panel}
\caption{CONV-TTL-BLO panel (front panel)}
\label{fp}
\end{center}
\end{figure}
\subsubsection{System status LEDs}
In the current version of the CONV-TTL-BLO boards, only several of the system status LEDs
present on the board are used, due to limited firmware support in the FPGA.
The implemented LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented
system status LEDs are off by default.
\begin{table}
\caption{System status LEDs on CONV-TTL-BLO front panels}
\label{tbl:status-leds}
\centerline
{
\begin{tabular}{l p{.75\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{LED}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{PW} & Power LED. Lights \textit{green} when a valid CONV-TTL-BLO firmware is loaded
to the FPGA. \\
\textit{ERR} & Error LED. Lights \textit{red} when no rear transition module board is present. \\
\textit{TTL\_N} & Negated-TTL status LED. Lights \textit{green} when negated TTL logic is selected
via the 8$^{th}$ position of the on-board selection switch. \\
% \textit{I2C} & I$^2$C status LED. Lights \textit{red} until an I$^2$C transfer has taken place. Once
% either a read or a write is successfully completed, the I$^2$C status LED lights \textit{green}
% to signal the communication is up. \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{SFP connector}
This connector is used to add White Rabbit support to the CONV-TTL-BLO boards.
If an optic fibre cable is connected to this socket, White Rabbit precise
time-stamping can be added to CONV-TTL-BLO. Four status LEDs above the connector are provisioned to
show the status of the White Rabbit link.
White Rabbit is currently not supported in the CONV-TTL-BLO firmware.
\subsubsection{TTL triggers}
One side of the dual LEMO 00 (type EPY) connector on the CONV-TTL-BLO boards
are used for the TTL trigger inputs. By connecting an external trigger source to
one of these connectors, a Blocking pulse is generated at the rear panel and
a TTL-level pulse is generated at the front panel. The triggers can be either
TTL, or INV-TTL level.
All input channels are line-terminated with 50$\Omega$ resistors.
\subsubsection{Repeated TTL pulses}
The other side of the dual LEMO 00 connector is used to output a TTL-level replica of the blocking
pulse received at the rear panel, or of the trigger signal arrived on the front panel.
The pulse width of this output is similar to the pulse output in the rear panel;
the rise time and top pulse level are however different from the Blocking output.
When the pulse is output, the LED of the corresponding channel blinks for 96~ms.
TTL output lines are not internally terminated.
\subsubsection{General purpose}
Four dedicated inverted-TTL connectors can be found in the lower part of the front panel.
Inverted-TTL outputs are not internally terminated.
\subsection{Rear panel}
The rear panel on CONV-TTL-BLO-RTM boards is shown in Fig.~\ref{fig:rear-panel}. It contains the
input and output connectors, as well as pulse status LEDs for six blocking-level pulse channels. A blocking-level
pulse at the input connector of a channel is repeated at the three outputs of the same channel in
blocking level and TTL level at the output connector of the corresponding channel on the front panel.
When a pulse is repeated on the output connector of a channel, the pulse status LED is lit for 96~ms.
\begin{figure}
\begin{center}
\includegraphics[scale=.55, keepaspectratio]{fig/rear-panel}
\caption{CONV-TTL-BLO-RTM panel (rear panel)}
\label{fig:rear-panel}
\end{center}
\end{figure}
%======================================================================================
% SEC: Pulse signals
%======================================================================================
\section{Output Pulse Signal}
\label{sec:pulse-def}
In order for CONV-TTL-BLO boards to work as repeaters, logic is implemented in the
on-board FPGA that reacts to a trigger at either rear or front panel and generates a
pulse at the output.
Extensive work was made by Carlos Gil-Soriano to research existing boards at CERN and
define a standard for pulse levels in repeater boards \cite{StandardBlocking}. Based on
this document and on further tests with two of the existing repeater boards at CERN, output
pulse widths and amplitudes were selected for the converter boards.
Three types of pulses are defined in the context of CONV-TTL-BLO boards. They
differ only in signal amplitude and signal rise and fall times, due to the circuitry
used to generate them; pulse widths are the same for all three types. Table~\ref{tbl:pulse-levels}
presents the different types of pulses and Fig.~\ref{fig:pulse-def} shows a graphic representation of
the pulse signal.
\begin{table}[h]
\caption{Trigger sources}
\label{tbl:pulse-levels}
\centerline
{
\begin{tabular}{l c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Type}} & \textbf{Pk-pk amplitude} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
TTL & 3.3~V & \\
INV-TTL & 3.3~V & Inverted version of TTL pulse \\
Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
\hline
\end{tabular}
}
\end{table}
\begin{figure}[h]
\begin{center}
\includegraphics{fig/pulse-def}
\caption{Pulse signal shape}
\label{fig:pulse-def}
\end{center}
\end{figure}
%\begin{table}[h]
%\caption{Pulse signal characteristics}
%\label{tbl:pulse-def}
%\centerline
%{
% \begin{tabular}{c c p{.5\textwidth}}
% \hline
% \textbf{Symbol} & \textbf{Value} & \multicolumn{1}{c}{\textbf{Description}} \\
% \hline
% $t_w$ & 1~$\mu$s & Pulse width \\
% $t_{p,min}$ & \textcolor{red}{\textbf{!!!}} & Minimum period of pulse signal \\
% \hline
% \end{tabular}
%}
%\end{table}
%======================================================================================
% SEC: Boards
%======================================================================================
%\section{Converter Boards}
%\label{sec:boards}
%This section gives further information about the three boards which when coupled together
%can be used to replicate blocking-level pulses.
%
%\subsection{CONV-TTL-BLO}
%\label{sec:conv-ttl-blo}
%A picture of the CONV-TTL-BLO mainboard is presented in Fig.~\ref{fig:conv-ttl-blo}.
%This board represents the main part of the converter system; all of the active circuitry
%involved in pulse repetition is present on this board. The Spartan-6 FPGA is the core part
%of the board, reacting to pulses at either the TTL inputs arriving on front panels, or
%blocking pulses arriving on rear panels through the RTM system, and generating pulses for
%the output channels, both blocking and TTL.
%
%\textcolor{red}{\textbf{board picture}}
%
%\subsubsection{TTL and INV-TTL inputs}
%\label{sec:ttl-inp}
%
%TTL and INV-TTL level pulses arrive through the LEMO connectors. The pulses are passed
%through a Schmitt trigger buffer circuit to smooth out transitions and then passed to the FPGA.
%The buffer circuit is shown in Fig.~\ref{fig:ttl-inp} and is common to the six TTL input channels
%and the four INV-TTL input channels.
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=.85\textwidth]{fig/ttl-inp.png}
% \caption{TTL and INV-TTL input circuit}
% \label{fig:ttl-inp}
%\end{center}
%\end{figure}
%
%Since a signal at the input can be both TTL and INV-TTL, a switch (called the \textit{LEVEL} switch)
%is provided on the board to select between the two. The switch (shown in Fig.~\ref{fig:level-switch})
%is checked in the FPGA logic and the output pulse per each channel is adjusted according to its status.
%
%As can be seen in Fig.~\ref{fig:level-switch}, when the switch is in the upper position, it indicates
%that the signal on TTL and INV-TTL inputs is TTL level. When the switch is in the lower position,
%this indicates an INV-TTL level at TTL and INV-TTL inputs.
%
%\textcolor{red}{\textbf{LEVEL switch pic}}
%
%A board can only have TTL \textit{or} INV-TTL inputs at one time on \textit{any} channel, not both.
%The LEVEL switch indicates which of the two it is. Since there is only one LEVEL switch on CONV-TTL-BLO
%boards, it is not possible to set the type of signal per each channel.
%
%\subsubsection{Blocking inputs}
%\label{sec:blo-inp}
%
%After their arrival in the rear panel through the RTMP LEMO connectors, blocking pulses pass through an
%input circuit, shown in Fig.~\ref{fig:blo-inp}. This circuit's function is to adjust the voltage level
%of the blocking pulse to a level more suitable for input to the FPGA. A transient voltage suppressing
%diode at the input offers protection against any voltage spikes at the input, while the optocoupler
%provides the voltage adjustment.
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=\textwidth]{fig/blo-inp.png}
% \caption{Blocking input circuit}
% \label{fig:blo-inp}
%\end{center}
%\end{figure}
%
%Signal levels expected at the input match those of the blocking standard definition \cite{StandardBlocking}.
%\textcolor{red}{\textbf{The minimum signal level that the optocoupler is sensitive to is 5~V.}}
%
%The output of this circuit is further passed through a Schmitt-trigger buffer to smooth out transitions.
%Since the buffer is the same inverting buffer present in the TTL input circuits, the inverted pulse signal
%coming out of the circuit in Fig.~\ref{fig:blo-inp} is once again inverted, and the FPGA receives the
%recovered pulse signal in normal polarity.
%
%\subsubsection{Blocking outputs}
%\label{sec:blo-outp}
%The blocking output circuit is shown in Fig.~\ref{fig:blo-outp}. The circuit is a typical flyback topology \cite{flyback},
%with the Coilcraft inductor providing a galvanically isolated pulse at the output. Rise and fall times of
%the pulse signals are controlled mainly by the resistors at the gate of the MOSFET transistor.
%
%\textcolor{red}{\textbf{operation}}
%
%\textcolor{red}{\textbf{snubber circuit design}}
%
%\textcolor{red}{\textbf{max pulse length on the circuit}}
%
%\begin{figure}[h]
% \begin{center}
% \includegraphics[width=\textwidth]{fig/blo-outp.png}
% \caption{Blocking output circuit}
% \label{fig:blo-outp}
% \end{center}
%\end{figure}
%======================================================================================
% SEC: FPGA Logic
%======================================================================================
\section{FPGA Logic}
\label{sec:fpga}
\subsection{Block diagram}
\label{sec:fpga-bd}
A block diagram of the FPGA design is presented in Fig.~\ref{fig:fpga-bd}. First, an internal clock signal
is generated from the on-board differential 125~MHz clock oscillator. This internal clock signal is used as
the clock for all synchronous logic internal to the FPGA.
\begin{figure}
\begin{center}
\includegraphics[width=\textwidth]{fig/fpga-bd}
\caption{Block diagram of FPGA logic design}
\label{fig:fpga-bd}
\end{center}
\end{figure}
The \textit{reset\_gen} module generates an internal active-low reset signal that is input to all
synchronous with reset. RTM presence is detected via the \textit{rtm\_detector} module. Signals
generated by this module can be used in various ways in the design; in the current version of the design,
they are used as control signals for one of the bicolor LEDs on the board (the \textit{ERR} LED).
Bicolor LEDs on the board are controlled via the \textit{bicolor\_led\_ctrl} module. Based on input
control signals, this module generates signals at a preset refresh rate to light the various status LEDs
on board.
Finally, the \textit{pulse\_generator} modules generate predefined-width pulses to be transmitted on the
blocking, TTL and INV-TTL channels. The same \textit{pulse\_generator} module with a different pulse width
is used to light the pulse arrival LEDs on front an rear panels.
\subsection{Reset generation}
\label{sec:fpga-rst}
\begin{table}[h]
\caption{\textit{reset\_gen} module generics and ports}
\label{tbl:fpga-rst-gen}
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{g\_reset\_time} & Reset time, in number of \textit{clk\_i} clock cycles \\
\textit{clk\_i} & Input clock signal \\
\textit{rst\_n\_o} & Output reset signal, active-low \\
\hline
\end{tabular}
}
\end{table}
The reset generator module (\textit{reset\_gen}) implemented inside the FPGA is responsible with generating
a predefined-width reset signal when power is applied to the FPGA.
When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen} module starts
counting up. While this counter is counting up, the active-low reset signal is kept low, resetting
synchronous logic inside the FPGA. When the counter reaches the value of the reset width (specified via the
\textit{g\_reset\_time} generic at synthesis time), the reset signal is de-asserted, the counter is
disabled and the \textit{reset\_gen} module remains inactive until the next power-on reset.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different FPGA architecture is not
guaranteed to provide the same results. The \textit{reset\_gen} module has an initial value set for the counter
signal after power-up, which is guaranteed by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 96~ms.
\subsection{RTM detection}
\label{sec:fpga-rtm-det}
\begin{table}[h]
\caption{\textit{rtm\_detector} module generics and ports}
\label{tbl:fpga-rtm-detector}
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{rtmm\_i} & Input from RTMM detection lines \\
\textit{rtmp\_i} & Input from RTMP detection lines \\
\textit{rtmm\_ok\_o} & Status of RTMM lines (\textit{high} means RTMM plugged in) \\
\textit{rtmp\_ok\_o} & Status of RTMP lines (\textit{high} means RTMP plugged in) \\
\hline
\end{tabular}
}
\end{table}
A simple RTM detection mechanism is employed on CONV-TTL-BLO boards. Three lines on the VME P2 connector are dedicated
for RTMM detection, and three lines for RTMP detection. On the CONV-TTL-BLO side, these lines are pulled up to VCC with
pull-up resistors. Thus, when no RTMM is plugged in, all six lines (RTMM and RTMP) are logic high due to the pull-up.
When an RTM is plugged in, the lines corresponding to the RTMM/P is connected to ground and a logic low will be detected
at the FPGA input.
The \textit{rtm\_detector} module simply sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the \textit{rtmm\_i} and
\textit{rtmp\_i} input signals are respectively all-ones.
While more advanced RTM detection can be employed if need be, the RTM signals are currently used to signal an error via the
\textit{ERR} status LED on the CONV-TTL-BLO front panel. The \textit{ERR} led is lit when both \textit{rtmp\_ok} and \textit{rtmm\_ok}
outputs are low.
\subsection{Pulse generation}
\label{sec:fpga-pulse-gen}
\begin{table}[h]
\caption{\textit{pulse\_generator} module generics and ports}
\label{tbl:fpga-pulse-generator}
\centerline
{
\begin{tabular}{p{.15\textwidth} p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port/generic}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{g\_pulse\_width} & Width of the pulse, in number of \textit{clk\_i} clock cycles \\
\textit{g\_glitch\_filt\_len} & Length of glitch filter. A length of \textit{1} means the
pulse generator block is sensitive to glitches of more than one
clock cycle \\
\textit{clk\_i} & Clock input \\
\textit{rst\_n\_i} & Active-low reset signal \\
\textit{trig\_i} & Trigger signal, must be active-high \\
\textit{pulse\_o} & Active-high pulse signal \\
\hline
\end{tabular}
}
\end{table}
The \textit{pulse\_generator} module is used to generate pulses of predefined width based on a trigger input.
To avoid glitches on the input, the trigger input is taken through a variable-length glitch filter (set by
the user at synthesis time via the \textit{g\_glitch\_filt\_len} generic). The glitch filter consists of a
series of flip-flops that, when all high, trigger the generation of a variable-width pulse at the output.
The width of the pulse is set via the \textit{g\_pulse\_width} generic.
Assuming active-high triggers arrive at the \textit{pulse\_generator} module trigger input, high-level active pulses
are generated at the pulse output of the module (Fig.~\ref{fig:pulse-gen-sigs}). In order to avoid output jitter,
the pulse output is selected between the trigger input and the internally-generated pulse signal. The latter
is generated using an internal counter, which starts counting once the glitch filter has settled to all-ones.
When a trigger arrives at the input it is directed to the output; when the glitch filter settles to all-ones,
the pulse signal at the input is extended to the pulse width value set by the \textit{g\_pulse\_width} generic.
\begin{figure}
\begin{center}
\includegraphics{fig/pulse-gen-sigs}
\caption{Pulse generator trigger and output polarity}
\label{fig:pulse-gen-sigs}
\end{center}
\end{figure}
Finally, because the \textit{pulse\_generator} module is used to drive the transformers generating the blocking pulses, a
pulse rejection mechanism is employed. This mechanism rejects pulses longer than the desired output pulse width by setting
a signal that is used to select the signal routed to the output. The pulse rejection signal is set as soon as a pulse is
generated via the internal counter, thus once the input has passed through the glitch filter successfully. The pulse
rejection signal is cleared when the trigger input settles back to zero and the cycle restarts when a new input pulse
arrives. It is assumed that the input pulse frequency is sufficiently low to allow the transformer to
give away all the energy stored in its magnetic field.
Multiple \textit{pulse\_generator} modules are instantiated in the design and used to generate pulse signals. Six of these
are configured to output 1~$\mu$s pulses on both TTL and blocking outputs based on a trigger signal which is the \textit{OR}
of TTL and blocking level input pulses. Four are configured to output 1~$\mu$s pulses based on a trigger from the INV-TTL channels.
Finally, six \textit{pulse\_generator} modules are configured to output 96~ms pulses to light the pulse status LEDs corresponding to the six
blocking and TTL channels; they are sensitive to the same trigger input as the TTL and blocking pulse generators.
All pulse generator modules instantiated in the design have glitch filters with length four, thus the input trigger pulse
should have a width of at least 32~ns, considering the 125~MHz clock input.
%======================================================================================
% SEC: Internal regs
%======================================================================================
%\pagebreak
%\section{Accessing internal registers}
%\label{sec:internal-regs}
%
%\subsection{ELMA crates}
%CONV-TTL-BLO boards have been designed to operate in ELMA crates. These crates provide a
%back plane with VME64x connectors which boards can be plugged into. A dedicated board inside the
%ELMA crates called the SysMon (System Monitor) monitors overall system status and provides access
%to boards plugged into the VME back plane.
%
%The user can connect to SysMon boards either through a simple RS-232 interface, or through Telnet.
%In order to send commands to a board plugged into an ELMA crate, the user would connect to the SysMon
%over one of these two interfaces and send \verb=readreg= and \verb=writereg= commands to
%board-specific registers, as exemplified in Section \ref{sec:getting-started} to control their functioning.
%
%%Since it is the interface most experimented with up to the point of writing of this document,
%%only the Telnet interface is used throughout this document.
%
%\subsection{Board Addressing}
%\label{sec:brd-addressing}
%
%Communication with the CONV-TTL-BLO FPGA is done via I$^2$C interface through the SERA and SERB pins
%in P1 VME64x connectors. In order to access a CONV-TTL-BLO board, it is necessary to send:
%
%\begin{itemize}
% \item The board's 7-bit I$^2$C address. Every CONV-TTL-BLO has an address that prepends two bits
% of value \textit{10} to the Geographical Address of the slot according to VME64x specifications.
% \item An internal CONV-TTL-BLO register address. It is a 16-bit integer in \textit{little endian} format
% (most significant byte is sent first).
%\end{itemize}
%
%After this, four bytes of data are read/written from/to the internal CONV-TTL-BLO register. These
%four bytes of data are written in \textit{big endian} format (least significant byte is sent first).
%
%The addressing protocol is thoroughly described in \cite{sysmon-i2c}. The SysMon acts as a master on the
%I$^2$C interface and has the protocol implemented as software on the on-board processor. The FPGAs on
%CONV-TTL-BLO boards implement an I$^2$C slave and decode the data streams sent by the SysMon.
%
%
%\subsection{CONV-TTL-BLO memory map}
%\label{sec:memmap}
%
%Table \ref{tbl:memmap} summarizes the registers mapping in the current version of the CONV-TTL-BLO firmware.
%The first column represents the Wishbone address internal to the FPGA firmware and the second column represents
%the ELMA register address (in \verb=readreg= and \verb=writereg= commands).
%
%\begin{table}[!hbtp]
%\caption{Memory map of the CONV-TTL-BLO design}
%\label{tbl:memmap}
%\centerline
%{
% \begin{tabular}{ r r l c p{.5\textwidth} }
% \hline
% \multicolumn{1}{c}{Address} & \multicolumn{1}{c}{ELMA} & \multicolumn{1}{c}{Name} & \multicolumn{1}{c}{Access} & \multicolumn{1}{c}{Description} \\
% \hline
% 0x00 & 1 & STAT\_L & R & Lower 32 bits of system status register \\
% 0x04 & 2 & STAT\_H & R & Upper 32 bits of system status register \\
% 0x40 & 17 & I2C\_CTR0 & R & I$^2$C control register \\
% 0x44 & 18 & I2C\_LT & R & I$^2$C line timing register, provides the current I$^2$C line speed \\
% 0x48 & 19 & I2C\_DTX & R/W & Data to transmit through the I$^2$C interface \\
% 0x4C & 20 & I2C\_DRXA & R & Lower 32 bits of data received through the I$^2$C interface \\
% 0x50 & 21 & I2C\_DRXB & R & Upper 32 bits of data received through the I$^2$C interface \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsection{Register description}
%
%
%\subsubsection{STAT\_L}
%
%\begin{table}[H]
%%\caption{STAT\_L register}
%%\label{tbl:reg-statl}
%\centerline
%{
% \begin{tabular}{r c c p{.6\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & IDENT\_L & 0x00000000 & Lower 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%
%
%\subsubsection{STAT\_H}
%
%\begin{table}[H]
%%\caption{STAT\_H register}
%%\label{tbl:reg-stath}
%\centerline
%{
% \begin{tabular}{r c c p{.6\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
% \hline
% 15..0 & IDENT\_H & 0x0000 & Upper 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
% 18..16 & RTMM & "000" & Rear transition module mainboard (RTMM) identification \cite{rtm-ident} \\
% 21..19 & RTMP & "000" & Rear transition module piggyback (RTMP) identification \cite{rtm-ident} \\
% 31..22 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%
%\subsubsection{I2C\_CTR0}
%\begin{table}[H]
%%\caption{I2C\_CTR0 register}
%%\label{tbl:reg-i2c-ctr0}
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 0 & I2C\_OP & '0' & I$^2$C operation, unused bit \\
% 7..1 & I2C\_ADDR & see Sec. \ref{sec:brd-addressing} & I$^2$C address of the CONV-TTL-BLO board \\
% 11..8 & BIA & 0x2 & Bytes of Indirect Addressing \\
% 19..12 & BRD & 0x4 & Bytes to be read from FPGA \\
% 27..20 & BWR & 0x4 & Bytes to be written to FPGA \\
% 31..28 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_LT}
%\begin{table}[H]
%%\caption{I2C\_LT register}
%%\label{tbl:reg-i2c-ctr0}
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 7..0 & WBCP & 20 & WishBone Clock Period, in ns \\
% 31..8 & SCLP & 0x000000 & SCL Period \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DTX}
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DTX & 0x00000000 & DTX register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DRXA}
%
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DRXA & 0x00000000 & DRXA register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DRXB}
%
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DRXB & 0x00000000 & DRXB register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{ug-conv-ttl-blo}
\end{document}
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\begin{titlepage}
\vspace*{3cm}
\noindent{\LARGE \textbf{CONV-TTL-BLO User Guide}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo.png}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/ug/ug-conv-ttl-blo.tex
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......@@ -4,13 +4,19 @@
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
......@@ -19,23 +25,7 @@
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\title{
\textbf{
CONV-TTL-BLO \\
User Guide}
}
\author{Theodor-Adrian Stana}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25]{fig/cern-logo.png}
\end{center}
\end{figure}
\maketitle{}
\pagebreak
\include{title}
%------------------------------------------------------------------------------
% Revision history
......@@ -49,8 +39,9 @@ User Guide}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
2013-06-19 & 1.00 & First version \\
2013-06-21 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
19-06-2013 & 1.00 & First version \\
21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
25-06-2013 & 1.02 & New title page and page layout \\
\hline
\end{tabular}
}
......@@ -77,11 +68,12 @@ User Guide}
VME & VERSAmodule Eurocard \\
\end{tabular}
\pagebreak
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
......@@ -269,11 +261,9 @@ load.
When a pulse is repeated on the output connector of a channel, the pulse status LED flashes briefly.
\begin{figure}[htbp]
\begin{center}
\includegraphics[scale=.55, keepaspectratio]{fig/rear-panel}
\centerline{\includegraphics[scale=.75]{fig/rear-panel}}
\caption{CONV-TTL-BLO-RTM panel (rear panel)}
\label{fig:rear-panel}
\end{center}
\end{figure}
%======================================================================================
......
hdl/elma_i2c/doc/elma_i2c/Makefile
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FILE=elma_i2c
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
......
hdl/elma_i2c/doc/elma_i2c/elma_i2c.tex
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......@@ -4,39 +4,70 @@
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
\title{VME64x I$^2$C to Wishbone bridge}
\author
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
Theodor-Adrian Stana \\
CERN, BE-CO-HT \\
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
25-06-2013 & 1.00 & First version \\
\hline
\end{tabular}
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}
\begin{center}
\includegraphics[scale=.25,keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
% Break page
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
\section*{List of Abbreviations}
\begin{tabular}{l l}
FSM & Finite-State Machine \\
I$^2$C & Inter-Integrated Circuit (bus) \\
SysMon & ELMA crate System Monitor board \\
VME & VERSAmodule Eurocard \\
\end{tabular}
% Generate TOC and pagebreak after it
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%==============================================================================
% SEC: Intro
......@@ -44,7 +75,7 @@ CERN, BE-CO-HT \\
\section{Introduction}
\label{sec:intro}
This document describes the \textit{vme64x\_i2c} module, an I$^2$C to Wishbone
This document describes the \textit{elma\_i2c} module, an I$^2$C to Wishbone
bridge for the VME64x crates. The module implements an I$^2$C slave and translates
the protocol defined by ELMA in \cite{sysmon-i2c} into Wishbone accesses to a
Wishbone slave device.
......@@ -95,7 +126,7 @@ are sent by the VME board in big-endian order.
\label{sec:implem}
In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module
is instantiated and used within the \textit{vme64x\_i2c} module. The outputs of
is instantiated and used within the \textit{elma\_i2c} module. The outputs of
the \textit{i2c\_slave} module \textcolor{red}{REFERENCE?} are used as controls
for an eight-state finite state machine (FSM), a simplified version of which
is shown in Fig.~\ref{fig:fsm}. Table~\ref{tbl:fsm} also lists the states of
......@@ -103,31 +134,19 @@ the state machine.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth, keepaspectratio]{fig/fsm}}
\caption{Main FSM of \textit{vme64x\_i2c} module}
\caption{Main FSM of \textit{elma\_i2c} module}
\label{fig:fsm}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{vme64x\_i2c}}
\label{fig:sysmon-wr-fsm}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd-fsm}}
\caption{FSM states when the SysMon reads from the \textit{vme64x\_i2c}}
\label{fig:sysmon-rd-fsm}
\end{figure}
When the \textit{i2c\_slave} module finishes a transfer (signaled by a \textit{done\_p\_o} pulse),
the status is checked and if it is as expected (e.g., a \textit{address good} in the
\textit{ST\_IDLE} state), the FSM advances to the next state. It should be noted that where the
SysMon appears in the state names, it indicates what the SysMon action is. For example, if the state
of the FSM is \textit{ST\_SYSMON\_WR}, this means the SysMon is writing and the \textit{vme64x\_i2c}
of the FSM is \textit{ST\_SYSMON\_WR}, this means the SysMon is writing and the \textit{elma\_i2c}
is reading.
\begin{table}[h]
\caption{\textit{vme64x\_i2c} state machine}
\caption{States of \textit{elma\_i2c} FSM}
\label{tbl:fsm}
\centerline
{
......@@ -143,12 +162,12 @@ is reading.
\textit{ST\_SIM\_WB\_TRANSF} \\
ST\_SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{ST\_OP} if Wishbone address exists (Wishbone
\textit{ack} received, or \textit{ST\_IDLE} otherwise (Wishbone \textit{err}
\textit{ack} received), or \textit{ST\_IDLE} otherwise (Wishbone \textit{err}
received) \\
ST\_OP & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{ST\_SYSMON\_RD\_WB} state
(SysMon is reading from \textit{vme64x\_i2c}), otherwise continue shifting
in bytes (SysMon writing to \textit{vme64x\_i2c}) \\
(SysMon is reading from \textit{elma\_i2c}), otherwise continue shifting
in bytes (SysMon writing to \textit{elma\_i2c}) \\
ST\_SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{ST\_SYSMON\_WR\_WB}\\
ST\_SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
......@@ -166,8 +185,14 @@ To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and
\ref{fig:sysmon-rd-fsm} can be consulted, where the state of the FSM is shown
during reads and writes from the SysMon.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{elma\_i2c}}
\label{fig:sysmon-wr-fsm}
\end{figure}
When reading from the SysMon (Fig.~\ref{fig:sysmon-wr-fsm}), the
\textit{vme64x\_i2c} module will wait in the \textit{ST\_IDLE} state while
\textit{elma\_i2c} module will wait in the \textit{ST\_IDLE} state while
the I$^2$C address is sent, then go to the \textit{ST\_WB\_ADR} state to
shift in the address. A Wishbone transfer is simulated and if the address
exists (a Wishbone \textit{ack} is received), the first byte is shifted in
......@@ -185,12 +210,18 @@ detects a different value of \textit{op\_o} and goes into the
executed, the value of the register is read and sent via I$^2$C in the
\textit{ST\_SYSMON\_RD} state.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd-fsm}}
\caption{FSM states when the SysMon reads from the \textit{elma\_i2c}}
\label{fig:sysmon-rd-fsm}
\end{figure}
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{vme64x_i2c}
\bibliography{elma_i2c}
\end{document}
hdl/elma_i2c/doc/elma_i2c/fig/sysmon-rd-fsm.svg
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hdl/elma_i2c/doc/elma_i2c/title.tex 0 → 100644
View file @ 41e314fe
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% title
%---------------------------------------------------------------
\noindent{\LARGE \textbf{ELMA I$^2$C to Wishbone bridge}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo.png}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
hdl/elma_i2c/doc/i2c_slave/Makefile
View file @ 41e314fe
......@@ -2,7 +2,7 @@ FILE=i2c_slave
all:
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bibtex *.aux
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
......
hdl/elma_i2c/doc/i2c_slave/fig/i2c-addr.svg deleted 100644 → 0
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hdl/elma_i2c/doc/i2c_slave/i2c_slave.tex
View file @ 41e314fe
......@@ -10,37 +10,70 @@
\usepackage{color}
% Header and footer customization
\usepackage{fancyhdr}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
\title{I$^2$C Slave Core}
\author
{
Theodor-Adrian Stana \\
CERN, BE-CO-HT \\
}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{title}
\date{\today}
\maketitle
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\begin{figure}
\begin{center}
\includegraphics[scale=.25,keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\section*{Revision history}
% Break page
\pagebreak
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
25-06-2013 & 1.00 & First version \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% Generate TOC and pagebreak after it
%------------------------------------------------------------------------------
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
\section*{List of Abbreviations}
\begin{tabular}{l l}
ASIC & Application-Specific Integrated Circuit \\
FPGA & Field-Programmable Gate Array \\
I$^2$C & Inter-Integrated Circuit \\
SCL & Serial CLock \\
SDA & Serial DAta \\
\end{tabular}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\section{Introduction}
\label{sec:intro}
......@@ -54,7 +87,7 @@ of the bits. The status of the module can be obtained via dedicated ports.
The main features of the \textit{i2c\_slave} module are:
\begin{itemize}
\item 7-bit addressing,
\item 7-bit addressing
\item standard (100~kHz) or fast (400~kHz) modes supported
\item no clock strething, all information provided by the module should be handled
externally within the time span of an I$^2$C bit transfer
......@@ -70,21 +103,20 @@ specification \cite{i2c-spec} defines all aspects of the protocol, from hardware
connections on the bus, to bit- and byte-level data transfers and electrical
characteristics of the bus. A summary about the widely-used protocol is given here.
Devices on the I$^2$C bus are connected together via two pins on the bus: the SCL
(serial clock) and SDA (serial data) pins. The I$^2$C bus uses a master-slave topology,
with I$^2$C masters driving the SCL line to send or receive bits on the SDA line. Both
the SCL and SDA lines on an I$^2$C device must be open-collector outputs.
As Figure~\ref{fig:i2c-bus} shows, one pull-up resistor on the bus connects the line to
VCC and I$^2$C devices connect the SCL and SDA lines to ground when they drive the lines.
In this way, a device can set a logic low level on the bus by driving the pin and a logic
high level by releasing the pin.
\begin{figure}[b]
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-bus}}
\caption{I$^2$C bus topology}
\label{fig:i2c-bus}
\end{figure}
Devices on the I$^2$C bus are connected together via two pins on the bus: the SCL
(serial clock) and SDA (serial data) pins. I$^2$C masters drive the SCL line to send or
receive bits on the SDA line. Both the SCL and SDA lines on an I$^2$C device are open-collector
pins; as Figure~\ref{fig:i2c-bus} shows, one pull-up resistor on the bus connects the line to
VCC and I$^2$C devices connect the SCL and SDA lines to ground when they drive the lines.
In this way, a device can set a logic low level on the bus by driving the pin and a logic
high level by releasing the pin.
A typical I$^2$C bit-level transfer (Figure~\ref{fig:i2c-bitlevel}) follows the following sequence:
\begin{itemize}
\item master sends a start condition, driving the SDA line low while the SCL line is high
......@@ -101,29 +133,17 @@ A typical I$^2$C bit-level transfer (Figure~\ref{fig:i2c-bitlevel}) follows the
\label{fig:i2c-bitlevel}
\end{figure}
Since there can be more than one slave on the bus, each bus is assigned an address to which
it responds when addressed. Two forms of addressing are defined in the I$^2$C bus specification,
a 7-bit addressing mode and a 10-bit addressing mode. Of the two, the 7-bit addressing mode is
the most widely used and also the only mode that the \textit{i2c\_slave} module supports.
A 7-bit address transfer is shown in Figure~\ref{fig:i2c-addr}. After sending the start condition,
the master sends the address MSB first, followed by an eighth bit stating whether the master
wishes to read from ('1') or write to ('0') the slave. An extra SCL cycle is issued by the master
after which should be used by the slave to acknolwedge (ACK -- '0') or not acknolwedge (NACK -- '1')
its address and signal its presence on the bus. If the master receives an NACK, it should abort
the transfer.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-addr}}
\caption{Sending of the address byte by the master}
\label{fig:i2c-addr}
\end{figure}
After a slave acknowledges its address, actual data transfer can begin. The following steps comprise
a complete I$^2$C data transfer (Figure~\ref{fig:i2c-transf}):
Data are transferred on the bus in bytes, one bit at a time starting with the most significant bit.
After each sent byte, the other communicating party ACKs~('0') or NACKs~('1') the transfer on a
9$^{th}$ SCL cycle. Any number of bytes can be sent during a transfer, the master decides when data
transfer should stop by sending the stop condition. The folowing steps comprise a complete I$^2$C
data transfer (Figure~\ref{fig:i2c-transf}):
\begin{itemize}
\item based on the R/W bit, the master either reads or writes a byte bit by bit from/to the
slave
\item master sends start condition
\item master sends slave address (7 bits of address + one R/W bit)
\item if a slave with this address exists, it ACKs ('0') the master
\item based on the R/W bit ('0' for read from slave, '1' for write to slave), the master either
reads or writes a byte bit by bit from/to the slave
\item the receiver ACKs ('0') or NACKs ('1') the byte on the ninth SCL cycle
\item any number of bytes may be sent, each followed by an ACK or NACK from the receiver
\item \textbf{optional:} the master may (or may not) reverse data transfer by issuing a repeated start and sending the
......@@ -156,7 +176,6 @@ tri-state buffers enabled by the \textit{scl\_en\_o} lines \textit{sda\_en\_o}.
\label{fig:i2c-ports}
\end{figure}
\pagebreak
To instantiate a tri-state buffer in VHDL:
\footnotesize
......@@ -222,7 +241,6 @@ regarding the various statuses.
%==============================================================================
% SEC: Operation
%==============================================================================
\pagebreak
\section{Operation}
\label{sec:oper}
......@@ -232,13 +250,12 @@ the \textit{i2c\_addr\_i} input, the \textit{done\_p\_o} output is set for one \
cycle and the \textit{stat\_o} output signals an address match. Based on the eighth
bit of the first I2C transfer byte, the module then starts shifting in or out each byte
in the transfer, setting the \textit{done\_p\_o} output for one clock cycle after each
received/sent byte. The \textit{stat\_o} output can be checked to see the byte has been
received/sent byte. The \textit{stat\_o} output can be checked to see if the byte has been
sent/received correctly.
As can be seen from the above description, \textit{done\_p\_o} is high after every completed
I$^2$C transfer. As a general rule, it should be checked periodically and when high, the
\textit{stat\_o} (possibly together with the \textit{op\_o}) output should be checked to see
the appropriate action to be taken. The various statuses possible at the
The \textit{done\_p\_o} set high after every completed transfer can be polled periodically and
when high, the \textit{stat\_o} (possibly together with the \textit{op\_o}) output can be checked
to see the appropriate action to be taken. The various statuses possible at the
\textit{stat\_o} output are listed in Table~\ref{tbl:stat}.
\begin{table}[h]
......@@ -326,42 +343,41 @@ Below are the steps which should be followed to write one or more bytes to a mas
This section presents implementation details of the \textit{i2c\_slave} module. A simplified
block diagram of the module is presented in Figure~\ref{fig:i2c-slave-bd}.
Deglitched versions of the SCL and SDA lines control operation of the central finite-state
machine (FSM), which sets the outputs and controls the rest of the components in the module.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-slave-bd}}
\caption{Block diagram of \textit{i2c\_slave} module}
\label{fig:i2c-slave-bd}
\end{figure}
Deglitched versions of the SCL and SDA lines control operation of the central finite-state
machine (FSM), which sets the outputs and controls the rest of the components in the module.
The FSM is sensitive to start and stop conditions and falling edges of the SCL line. It
controls how outputs are set, when the reception and transmission shift registers (RXSR/TXSR)
are loaded and when they shift, and acknowledging to the address and bytes sent by the
master. Table~\ref{tbl:fsm} lists the states of the FSM and the operations performed
in each state.
\begin{table}
\caption{\textit{i2c\_slave} module state machine}
\begin{table}[h]
\caption{The states of the \textit{i2c\_slave} FSM}
\label{tbl:fsm}
\centerline
{
\begin{tabular}{l p{.65\textwidth}}
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{IDLE} & Idle state, FSM default state after reset and the state returned to after
reception of a stop condition. \\
reception of a stop condition. \\
\textit{STA} & State reached after a start condition is received. On the falling edge
of SCL, the FSM transitions to \textit{ADDR} state. \\
of SCL, the FSM transitions to \textit{ADDR} state. \\
\textit{ADDR} & Shift in 7 address bits and R/W bit and go to \textit{ADDR\_ACK}
state. Each bit is shifted in on the falling edge of SCL. If the
received address matches, \textit{op\_o} is set and \textit{done\_p\_o}
as well. \\
\textit{ADDR\_ACK} & Check received address and send ACK if it corresponds to
\textit{i2c\_addr\_i}. If the R/W bit is high,
received address matches, \textit{op\_o} and \textit{done\_p\_o} are set. \\
\textit{ADDR\_ACK} & Check received address and send the ACK value at \textit{ack\_n\_i} if
the address corresponds to \textit{i2c\_addr\_i}. If the R/W bit is high,
go to \textit{RD} state, otherwise go to \textit{WR\_LOAD\_TXSR} state.
If received address does not match, NACK and go to \textit{IDLE}
If received address does not match, NACK and go to \textit{IDLE}
state. \\
\textit{RD} & Shift in eight bits sent by master and go to \textit{RD\_ACK} state. Each bit
is shifted in on the falling edge of SCL. When eight bits have been shifted in,
......@@ -374,9 +390,8 @@ in each state.
\textit{WR} & Shift out the eight bits of the TXSR starting with MSB and go to
\textit{WR\_ACK} state. TXSR shifts left on falling edge of SCL. When
eight bits have been shifted out, \textit{done\_p\_o} is set.\\
\textit{WR\_ACK} & Clear \textit{done\_p\_o}. Read ACK bit sent by master.
If '0', go back to \textit{WR} state, otherwise go to \textit{IDLE}
state. \\
\textit{WR\_ACK} & Read ACK bit sent by master. If '0', go back to \textit{WR} state, otherwise
go to \textit{IDLE} state. \\
\hline
\end{tabular}
}
......
hdl/elma_i2c/doc/i2c_slave/title.tex 0 → 100644
View file @ 41e314fe
\begin{titlepage}
\vspace*{3cm}
\noindent{\LARGE \textbf{I$^2$C Slave Core}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo.png}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
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